xref: /rk3399_rockchip-uboot/drivers/usb/cdns3/drd.h (revision 1a4f6af8bfd44c8ae6e87a81ff125eed47042cc5)
1*f6ce6072SVignesh Raghavendra /* SPDX-License-Identifier: GPL-2.0 */
2*f6ce6072SVignesh Raghavendra /*
3*f6ce6072SVignesh Raghavendra  * Cadence USB3 DRD header file.
4*f6ce6072SVignesh Raghavendra  *
5*f6ce6072SVignesh Raghavendra  * Copyright (C) 2018-2019 Cadence.
6*f6ce6072SVignesh Raghavendra  *
7*f6ce6072SVignesh Raghavendra  * Author: Pawel Laszczak <pawell@cadence.com>
8*f6ce6072SVignesh Raghavendra  */
9*f6ce6072SVignesh Raghavendra #ifndef __LINUX_CDNS3_DRD
10*f6ce6072SVignesh Raghavendra #define __LINUX_CDNS3_DRD
11*f6ce6072SVignesh Raghavendra 
12*f6ce6072SVignesh Raghavendra #include <linux/types.h>
13*f6ce6072SVignesh Raghavendra #include <linux/usb/otg.h>
14*f6ce6072SVignesh Raghavendra #include "core.h"
15*f6ce6072SVignesh Raghavendra 
16*f6ce6072SVignesh Raghavendra /*  DRD register interface for version v1. */
17*f6ce6072SVignesh Raghavendra struct cdns3_otg_regs {
18*f6ce6072SVignesh Raghavendra 	__le32 did;
19*f6ce6072SVignesh Raghavendra 	__le32 rid;
20*f6ce6072SVignesh Raghavendra 	__le32 capabilities;
21*f6ce6072SVignesh Raghavendra 	__le32 reserved1;
22*f6ce6072SVignesh Raghavendra 	__le32 cmd;
23*f6ce6072SVignesh Raghavendra 	__le32 sts;
24*f6ce6072SVignesh Raghavendra 	__le32 state;
25*f6ce6072SVignesh Raghavendra 	__le32 reserved2;
26*f6ce6072SVignesh Raghavendra 	__le32 ien;
27*f6ce6072SVignesh Raghavendra 	__le32 ivect;
28*f6ce6072SVignesh Raghavendra 	__le32 refclk;
29*f6ce6072SVignesh Raghavendra 	__le32 tmr;
30*f6ce6072SVignesh Raghavendra 	__le32 reserved3[4];
31*f6ce6072SVignesh Raghavendra 	__le32 simulate;
32*f6ce6072SVignesh Raghavendra 	__le32 override;
33*f6ce6072SVignesh Raghavendra 	__le32 susp_ctrl;
34*f6ce6072SVignesh Raghavendra 	__le32 reserved4;
35*f6ce6072SVignesh Raghavendra 	__le32 anasts;
36*f6ce6072SVignesh Raghavendra 	__le32 adp_ramp_time;
37*f6ce6072SVignesh Raghavendra 	__le32 ctrl1;
38*f6ce6072SVignesh Raghavendra 	__le32 ctrl2;
39*f6ce6072SVignesh Raghavendra };
40*f6ce6072SVignesh Raghavendra 
41*f6ce6072SVignesh Raghavendra /*  DRD register interface for version v0. */
42*f6ce6072SVignesh Raghavendra struct cdns3_otg_legacy_regs {
43*f6ce6072SVignesh Raghavendra 	__le32 cmd;
44*f6ce6072SVignesh Raghavendra 	__le32 sts;
45*f6ce6072SVignesh Raghavendra 	__le32 state;
46*f6ce6072SVignesh Raghavendra 	__le32 refclk;
47*f6ce6072SVignesh Raghavendra 	__le32 ien;
48*f6ce6072SVignesh Raghavendra 	__le32 ivect;
49*f6ce6072SVignesh Raghavendra 	__le32 reserved1[3];
50*f6ce6072SVignesh Raghavendra 	__le32 tmr;
51*f6ce6072SVignesh Raghavendra 	__le32 reserved2[2];
52*f6ce6072SVignesh Raghavendra 	__le32 version;
53*f6ce6072SVignesh Raghavendra 	__le32 capabilities;
54*f6ce6072SVignesh Raghavendra 	__le32 reserved3[2];
55*f6ce6072SVignesh Raghavendra 	__le32 simulate;
56*f6ce6072SVignesh Raghavendra 	__le32 reserved4[5];
57*f6ce6072SVignesh Raghavendra 	__le32 ctrl1;
58*f6ce6072SVignesh Raghavendra };
59*f6ce6072SVignesh Raghavendra 
60*f6ce6072SVignesh Raghavendra /*
61*f6ce6072SVignesh Raghavendra  * Common registers interface for both version of DRD.
62*f6ce6072SVignesh Raghavendra  */
63*f6ce6072SVignesh Raghavendra struct cdns3_otg_common_regs {
64*f6ce6072SVignesh Raghavendra 	__le32 cmd;
65*f6ce6072SVignesh Raghavendra 	__le32 sts;
66*f6ce6072SVignesh Raghavendra 	__le32 state;
67*f6ce6072SVignesh Raghavendra 	__le32 different1;
68*f6ce6072SVignesh Raghavendra 	__le32 ien;
69*f6ce6072SVignesh Raghavendra 	__le32 ivect;
70*f6ce6072SVignesh Raghavendra };
71*f6ce6072SVignesh Raghavendra 
72*f6ce6072SVignesh Raghavendra /* CDNS_RID - bitmasks */
73*f6ce6072SVignesh Raghavendra #define CDNS_RID(p)			((p) & GENMASK(15, 0))
74*f6ce6072SVignesh Raghavendra 
75*f6ce6072SVignesh Raghavendra /* CDNS_VID - bitmasks */
76*f6ce6072SVignesh Raghavendra #define CDNS_DID(p)			((p) & GENMASK(31, 0))
77*f6ce6072SVignesh Raghavendra 
78*f6ce6072SVignesh Raghavendra /* OTGCMD - bitmasks */
79*f6ce6072SVignesh Raghavendra /* "Request the bus for Device mode. */
80*f6ce6072SVignesh Raghavendra #define OTGCMD_DEV_BUS_REQ		BIT(0)
81*f6ce6072SVignesh Raghavendra /* Request the bus for Host mode */
82*f6ce6072SVignesh Raghavendra #define OTGCMD_HOST_BUS_REQ		BIT(1)
83*f6ce6072SVignesh Raghavendra /* Enable OTG mode. */
84*f6ce6072SVignesh Raghavendra #define OTGCMD_OTG_EN			BIT(2)
85*f6ce6072SVignesh Raghavendra /* Disable OTG mode */
86*f6ce6072SVignesh Raghavendra #define OTGCMD_OTG_DIS			BIT(3)
87*f6ce6072SVignesh Raghavendra /*"Configure OTG as A-Device. */
88*f6ce6072SVignesh Raghavendra #define OTGCMD_A_DEV_EN			BIT(4)
89*f6ce6072SVignesh Raghavendra /*"Configure OTG as A-Device. */
90*f6ce6072SVignesh Raghavendra #define OTGCMD_A_DEV_DIS		BIT(5)
91*f6ce6072SVignesh Raghavendra /* Drop the bus for Device mod	e. */
92*f6ce6072SVignesh Raghavendra #define OTGCMD_DEV_BUS_DROP		BIT(8)
93*f6ce6072SVignesh Raghavendra /* Drop the bus for Host mode*/
94*f6ce6072SVignesh Raghavendra #define OTGCMD_HOST_BUS_DROP		BIT(9)
95*f6ce6072SVignesh Raghavendra /* Power Down USBSS-DEV. */
96*f6ce6072SVignesh Raghavendra #define OTGCMD_DEV_POWER_OFF		BIT(11)
97*f6ce6072SVignesh Raghavendra /* Power Down CDNSXHCI. */
98*f6ce6072SVignesh Raghavendra #define OTGCMD_HOST_POWER_OFF		BIT(12)
99*f6ce6072SVignesh Raghavendra 
100*f6ce6072SVignesh Raghavendra /* OTGIEN - bitmasks */
101*f6ce6072SVignesh Raghavendra /* ID change interrupt enable */
102*f6ce6072SVignesh Raghavendra #define OTGIEN_ID_CHANGE_INT		BIT(0)
103*f6ce6072SVignesh Raghavendra /* Vbusvalid fall detected interrupt enable.*/
104*f6ce6072SVignesh Raghavendra #define OTGIEN_VBUSVALID_RISE_INT	BIT(4)
105*f6ce6072SVignesh Raghavendra /* Vbusvalid fall detected interrupt enable */
106*f6ce6072SVignesh Raghavendra #define OTGIEN_VBUSVALID_FALL_INT	BIT(5)
107*f6ce6072SVignesh Raghavendra 
108*f6ce6072SVignesh Raghavendra /* OTGSTS - bitmasks */
109*f6ce6072SVignesh Raghavendra /*
110*f6ce6072SVignesh Raghavendra  * Current value of the ID pin. It is only valid when idpullup in
111*f6ce6072SVignesh Raghavendra  *  OTGCTRL1_TYPE register is set to '1'.
112*f6ce6072SVignesh Raghavendra  */
113*f6ce6072SVignesh Raghavendra #define OTGSTS_ID_VALUE			BIT(0)
114*f6ce6072SVignesh Raghavendra /* Current value of the vbus_valid */
115*f6ce6072SVignesh Raghavendra #define OTGSTS_VBUS_VALID		BIT(1)
116*f6ce6072SVignesh Raghavendra /* Current value of the b_sess_vld */
117*f6ce6072SVignesh Raghavendra #define OTGSTS_SESSION_VALID		BIT(2)
118*f6ce6072SVignesh Raghavendra /*Device mode is active*/
119*f6ce6072SVignesh Raghavendra #define OTGSTS_DEV_ACTIVE		BIT(3)
120*f6ce6072SVignesh Raghavendra /* Host mode is active. */
121*f6ce6072SVignesh Raghavendra #define OTGSTS_HOST_ACTIVE		BIT(4)
122*f6ce6072SVignesh Raghavendra /* OTG Controller not ready. */
123*f6ce6072SVignesh Raghavendra #define OTGSTS_OTG_NRDY_MASK		BIT(11)
124*f6ce6072SVignesh Raghavendra #define OTGSTS_OTG_NRDY(p)		((p) & OTGSTS_OTG_NRDY_MASK)
125*f6ce6072SVignesh Raghavendra /*
126*f6ce6072SVignesh Raghavendra  * Value of the strap pins.
127*f6ce6072SVignesh Raghavendra  * 000 - no default configuration
128*f6ce6072SVignesh Raghavendra  * 010 - Controller initiall configured as Host
129*f6ce6072SVignesh Raghavendra  * 100 - Controller initially configured as Device
130*f6ce6072SVignesh Raghavendra  */
131*f6ce6072SVignesh Raghavendra #define OTGSTS_STRAP(p)			(((p) & GENMASK(14, 12)) >> 12)
132*f6ce6072SVignesh Raghavendra #define OTGSTS_STRAP_NO_DEFAULT_CFG	0x00
133*f6ce6072SVignesh Raghavendra #define OTGSTS_STRAP_HOST_OTG		0x01
134*f6ce6072SVignesh Raghavendra #define OTGSTS_STRAP_HOST		0x02
135*f6ce6072SVignesh Raghavendra #define OTGSTS_STRAP_GADGET		0x04
136*f6ce6072SVignesh Raghavendra /* Host mode is turned on. */
137*f6ce6072SVignesh Raghavendra #define OTGSTS_XHCI_READY		BIT(26)
138*f6ce6072SVignesh Raghavendra /* "Device mode is turned on .*/
139*f6ce6072SVignesh Raghavendra #define OTGSTS_DEV_READY		BIT(27)
140*f6ce6072SVignesh Raghavendra 
141*f6ce6072SVignesh Raghavendra /* OTGSTATE- bitmasks */
142*f6ce6072SVignesh Raghavendra #define OTGSTATE_DEV_STATE_MASK		GENMASK(2, 0)
143*f6ce6072SVignesh Raghavendra #define OTGSTATE_HOST_STATE_MASK	GENMASK(5, 3)
144*f6ce6072SVignesh Raghavendra #define OTGSTATE_HOST_STATE_IDLE	0x0
145*f6ce6072SVignesh Raghavendra #define OTGSTATE_HOST_STATE_VBUS_FALL	0x7
146*f6ce6072SVignesh Raghavendra #define OTGSTATE_HOST_STATE(p)		(((p) & OTGSTATE_HOST_STATE_MASK) >> 3)
147*f6ce6072SVignesh Raghavendra 
148*f6ce6072SVignesh Raghavendra /* OTGREFCLK - bitmasks */
149*f6ce6072SVignesh Raghavendra #define OTGREFCLK_STB_CLK_SWITCH_EN	BIT(31)
150*f6ce6072SVignesh Raghavendra 
151*f6ce6072SVignesh Raghavendra /* OVERRIDE - bitmasks */
152*f6ce6072SVignesh Raghavendra #define OVERRIDE_IDPULLUP		BIT(0)
153*f6ce6072SVignesh Raghavendra /* Only for CDNS3_CONTROLLER_V0 version */
154*f6ce6072SVignesh Raghavendra #define OVERRIDE_IDPULLUP_V0		BIT(24)
155*f6ce6072SVignesh Raghavendra 
156*f6ce6072SVignesh Raghavendra int cdns3_is_host(struct cdns3 *cdns);
157*f6ce6072SVignesh Raghavendra int cdns3_is_device(struct cdns3 *cdns);
158*f6ce6072SVignesh Raghavendra int cdns3_get_id(struct cdns3 *cdns);
159*f6ce6072SVignesh Raghavendra int cdns3_get_vbus(struct cdns3 *cdns);
160*f6ce6072SVignesh Raghavendra int cdns3_drd_init(struct cdns3 *cdns);
161*f6ce6072SVignesh Raghavendra int cdns3_drd_exit(struct cdns3 *cdns);
162*f6ce6072SVignesh Raghavendra int cdns3_drd_update_mode(struct cdns3 *cdns);
163*f6ce6072SVignesh Raghavendra int cdns3_drd_switch_gadget(struct cdns3 *cdns, int on);
164*f6ce6072SVignesh Raghavendra int cdns3_drd_switch_host(struct cdns3 *cdns, int on);
165*f6ce6072SVignesh Raghavendra 
166*f6ce6072SVignesh Raghavendra #endif /* __LINUX_CDNS3_DRD */
167