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Searched refs:sysctl (Results 1 – 3 of 3) sorted by relevance

/rk3399_rockchip-uboot/drivers/mmc/
H A Domap_hsmmc.c240 writel(readl(&mmc_base->sysctl) | SOFTRESETALL, &mmc_base->sysctl); in omap_hsmmc_init_setup()
242 while ((readl(&mmc_base->sysctl) & SOFTRESETALL) != 0x0) { in omap_hsmmc_init_setup()
260 mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK | CEN_MASK), in omap_hsmmc_init_setup()
262 mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK, in omap_hsmmc_init_setup()
265 while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) { in omap_hsmmc_init_setup()
271 writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl); in omap_hsmmc_init_setup()
294 mmc_reg_out(&mmc_base->sysctl, bit, bit); in mmc_reset_controller_fsm()
312 if (!(readl(&mmc_base->sysctl) & bit)) { in mmc_reset_controller_fsm()
314 while (!(readl(&mmc_base->sysctl) & bit)) { in mmc_reset_controller_fsm()
321 while ((readl(&mmc_base->sysctl) & bit) != 0) { in mmc_reset_controller_fsm()
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H A Dfsl_esdhc.c48 uint sysctl; /* System Control Register */ member
326 esdhc_clrsetbits32(&regs->sysctl, SYSCTL_TIMEOUT_MASK, timeout << 16); in esdhc_setup_data()
506 esdhc_write32(&regs->sysctl, esdhc_read32(&regs->sysctl) | in esdhc_send_cmd_common()
508 while (esdhc_read32(&regs->sysctl) & SYSCTL_RSTC) in esdhc_send_cmd_common()
512 esdhc_write32(&regs->sysctl, in esdhc_send_cmd_common()
513 esdhc_read32(&regs->sysctl) | in esdhc_send_cmd_common()
515 while ((esdhc_read32(&regs->sysctl) & SYSCTL_RSTD)) in esdhc_send_cmd_common()
559 esdhc_clrbits32(&regs->sysctl, SYSCTL_CKEN); in set_sysctl()
562 esdhc_clrsetbits32(&regs->sysctl, SYSCTL_CLOCK_MASK, clk); in set_sysctl()
569 esdhc_setbits32(&regs->sysctl, SYSCTL_PEREN | SYSCTL_CKEN); in set_sysctl()
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/rk3399_rockchip-uboot/arch/arm/include/asm/
H A Domap_mmc.h47 unsigned int sysctl; /* 0x12C */ member