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Searched refs:sample (Results 1 – 25 of 80) sorted by relevance

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/rk3399_rockchip-uboot/board/bosch/shc/
H A DKconfig52 activate, if you want to build for the B sample version
58 activate, if you want to build for the B2 sample version
64 activate, if you want to build for the C sample version
70 activate, if you want to build for the C2 sample version
76 activate, if you want to build for the C3 sample version
/rk3399_rockchip-uboot/drivers/sound/
H A Dsound.c13 const int sample = 48000; in sound_create_square_wave() local
15 const int period = freq ? sample / freq : 0; in sound_create_square_wave()
/rk3399_rockchip-uboot/doc/device-tree-bindings/exynos/
H A Dsound.txt10 - samsung,i2s-bits-per-sample : sample width, defalut is 16 bit
22 samsung,i2s-bits-per-sample = <16>;
H A Ddwmmc.txt30 Drv/sample clock selection register of corresponding channel.
33 . SelClk_sample: Select sample clock among 8 shifted clocks.
/rk3399_rockchip-uboot/cmd/ddr_tool/ddr_dq_eye/
H A Dddr_dq_eye.c94 u16 sample; in print_ddr_dq_eye() local
108 sample = fsp_result->min_val + in print_ddr_dq_eye()
117 if (i / PRINT_STEP == sample / PRINT_STEP) in print_ddr_dq_eye()
127 sample > min ? sample - min : 0, sample, in print_ddr_dq_eye()
128 max > sample ? max - sample : 0); in print_ddr_dq_eye()
/rk3399_rockchip-uboot/drivers/adc/
H A DKconfig28 - 600 KSPS of sample rate
46 - Up to 1MSPS of sample rate
55 - Up to 1MSPS of sample rate
/rk3399_rockchip-uboot/arch/x86/cpu/quark/
H A Dmrc_util.c1095 uint8_t sample; /* sample counter */ in find_rising_edge() local
1110 for (sample = 0; sample < SAMPLE_CNT; sample++) { in find_rising_edge()
1116 delay[bl] + sample * SAMPLE_DLY); in find_rising_edge()
1119 delay[bl] + sample * SAMPLE_DLY); in find_rising_edge()
1124 sample_result[sample] = sample_dqs(mrc_params, in find_rising_edge()
1129 rcvn ? "RCVN" : "WDQS", channel, rank, sample, in find_rising_edge()
1130 sample * SAMPLE_DLY, sample_result[sample]); in find_rising_edge()
1140 for (sample = 0; sample < SAMPLE_CNT; sample++) { in find_rising_edge()
1142 ((sample_result[sample] & (1 << bl)) >> bl) << in find_rising_edge()
1143 (SAMPLE_CNT - 1 - sample); in find_rising_edge()
/rk3399_rockchip-uboot/drivers/mmc/
H A Drockchip_dw_mmc.c146 static int rockchip_mmc_get_phase(struct dwmci_host *host, bool sample) in rockchip_mmc_get_phase() argument
159 if (sample) in rockchip_mmc_get_phase()
176 static int rockchip_mmc_set_phase(struct dwmci_host *host, bool sample, int degrees) in rockchip_mmc_set_phase() argument
241 if (sample) in rockchip_mmc_set_phase()
247 sample ? "sample" : "drv", degrees, delay_num, in rockchip_mmc_set_phase()
248 rockchip_mmc_get_phase(host, sample) in rockchip_mmc_set_phase()
370 static int rockchip_mmc_set_phase(struct dwmci_host *host, bool sample, int degrees) { return 0; } in rockchip_mmc_set_phase() argument
/rk3399_rockchip-uboot/arch/arm/dts/
H A Dexynos5250.dtsi87 samsung,i2s-bits-per-sample = <16>;
99 samsung,i2s-bits-per-sample = <16>;
H A Drk3036-sdk-u-boot.dtsi11 default-sample-phase = <0>;
H A Drk3128-u-boot.dtsi49 default-sample-phase = <0>;
H A Dsun8i-v3s.dtsi109 "sample";
128 "sample";
147 "sample";
/rk3399_rockchip-uboot/doc/device-tree-bindings/video/
H A Ddisplay-timing.txt31 sample data on falling edge
33 sample data on rising edge
/rk3399_rockchip-uboot/board/Marvell/guruplug/
H A Dkwbimage.cfg39 # bit27-24: 7= CL+2, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
111 # bit8 : 1 , add writepath sample stage, must be 1 for DDR freq >= 300MHz
/rk3399_rockchip-uboot/board/Seagate/dockstar/
H A Dkwbimage.cfg42 # bit27-24: 7= CL+2, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
114 # bit8 : 1 , add writepath sample stage, must be 1 for DDR freq >= 300MHz
/rk3399_rockchip-uboot/board/Synology/ds109/
H A Dkwbimage.cfg43 # bit27-24: 7= CL+2, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
115 # bit8 : 1 , add writepath sample stage, must be 1 for DDR freq >= 300MHz
/rk3399_rockchip-uboot/board/Marvell/dreamplug/
H A Dkwbimage.cfg40 # bit27-24: 7= CL+2, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
112 # bit8 : 1 , add writepath sample stage, must be 1 for DDR freq >= 300MHz
/rk3399_rockchip-uboot/board/Seagate/goflexhome/
H A Dkwbimage.cfg45 # bit27-24: 7= CL+2, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
117 # bit8 : 1 , add writepath sample stage, must be 1 for DDR freq >= 300MHz
/rk3399_rockchip-uboot/board/Marvell/sheevaplug/
H A Dkwbimage.cfg39 # bit27-24: 7= CL+2, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
111 # bit8 : 1 , add writepath sample stage, must be 1 for DDR freq >= 300MHz
/rk3399_rockchip-uboot/board/LaCie/netspace_v2/
H A Dkwbimage.cfg40 # bit27-24: 8= CL+3, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
111 # bit8 : 1 , add writepath sample stage, must be 1 for DDR freq >= 300MHz
H A Dkwbimage-is2.cfg40 # bit27-24: 8= CL+3, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
111 # bit8 : 1 , add writepath sample stage, must be 1 for DDR freq >= 300MHz
H A Dkwbimage-ns2l.cfg40 # bit27-24: 8= CL+3, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
111 # bit8 : 1 , add writepath sample stage, must be 1 for DDR freq >= 300MHz
/rk3399_rockchip-uboot/board/cloudengines/pogo_e02/
H A Dkwbimage.cfg43 # bit27-24: 7= CL+2, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
115 # bit8 : 1 , add writepath sample stage, must be 1 for DDR freq >= 300MHz
/rk3399_rockchip-uboot/board/raidsonic/ib62x0/
H A Dkwbimage.cfg40 # bit27-24: 0x7, CL+2, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
112 # bit8: 0x1, add writepath sample stage, must be 1 for DDR freq >= 300MHz
/rk3399_rockchip-uboot/board/keymile/km_arm/
H A Dkwbimage.cfg60 # bit27-24: 6= CL+3, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
123 # bit8 : 0 , no sample stage

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