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Searched refs:rval (Results 1 – 16 of 16) sorted by relevance

/rk3399_rockchip-uboot/drivers/gpio/
H A Dtegra186_gpio.c50 uint32_t rval; in tegra186_gpio_set_out() local
53 rval = readl(reg); in tegra186_gpio_set_out()
55 rval &= ~TEGRA186_GPIO_OUTPUT_CONTROL_FLOATED; in tegra186_gpio_set_out()
57 rval |= TEGRA186_GPIO_OUTPUT_CONTROL_FLOATED; in tegra186_gpio_set_out()
58 writel(rval, reg); in tegra186_gpio_set_out()
61 rval = readl(reg); in tegra186_gpio_set_out()
63 rval |= TEGRA186_GPIO_ENABLE_CONFIG_OUT; in tegra186_gpio_set_out()
65 rval &= ~TEGRA186_GPIO_ENABLE_CONFIG_OUT; in tegra186_gpio_set_out()
66 rval |= TEGRA186_GPIO_ENABLE_CONFIG_ENABLE; in tegra186_gpio_set_out()
67 writel(rval, reg); in tegra186_gpio_set_out()
[all …]
/rk3399_rockchip-uboot/drivers/mtd/nand/raw/
H A Dnand_util.c481 int rval; in nand_verify_page_oob() local
494 rval = mtd_read_oob(mtd, ofs, &vops); in nand_verify_page_oob()
495 if (!rval) in nand_verify_page_oob()
496 rval = memcmp(ops->datbuf, vops.datbuf, vops.len); in nand_verify_page_oob()
497 if (!rval) in nand_verify_page_oob()
498 rval = memcmp(ops->oobbuf, vops.oobbuf, vops.ooblen); in nand_verify_page_oob()
502 return rval ? -EIO : 0; in nand_verify_page_oob()
521 int rval = 0; in nand_verify() local
533 rval = nand_read(mtd, verofs, &verlen, verbuf); in nand_verify()
534 if (!rval || (rval == -EUCLEAN)) in nand_verify()
[all …]
/rk3399_rockchip-uboot/arch/arm/mach-sunxi/
H A Dclock_sun4i.c202 uint32_t rval = readl(&ccm->pll3_cfg); in clock_get_pll3() local
203 int m = ((rval & CCM_PLL3_CTRL_M_MASK) >> CCM_PLL3_CTRL_M_SHIFT); in clock_get_pll3()
211 uint32_t rval = readl(&ccm->pll5_cfg); in clock_get_pll5p() local
212 int n = ((rval & CCM_PLL5_CTRL_N_MASK) >> CCM_PLL5_CTRL_N_SHIFT); in clock_get_pll5p()
213 int k = ((rval & CCM_PLL5_CTRL_K_MASK) >> CCM_PLL5_CTRL_K_SHIFT) + 1; in clock_get_pll5p()
214 int p = ((rval & CCM_PLL5_CTRL_P_MASK) >> CCM_PLL5_CTRL_P_SHIFT); in clock_get_pll5p()
222 uint32_t rval = readl(&ccm->pll6_cfg); in clock_get_pll6() local
223 int n = ((rval & CCM_PLL6_CTRL_N_MASK) >> CCM_PLL6_CTRL_N_SHIFT); in clock_get_pll6()
224 int k = ((rval & CCM_PLL6_CTRL_K_MASK) >> CCM_PLL6_CTRL_K_SHIFT) + 1; in clock_get_pll6()
H A Dclock_sun6i.c300 uint32_t rval = readl(&ccm->pll3_cfg); in clock_get_pll3() local
301 int n = ((rval & CCM_PLL3_CTRL_N_MASK) >> CCM_PLL3_CTRL_N_SHIFT) + 1; in clock_get_pll3()
302 int m = ((rval & CCM_PLL3_CTRL_M_MASK) >> CCM_PLL3_CTRL_M_SHIFT) + 1; in clock_get_pll3()
312 uint32_t rval = readl(&ccm->pll6_cfg); in clock_get_pll6() local
313 int n = ((rval & CCM_PLL6_CTRL_N_MASK) >> CCM_PLL6_CTRL_N_SHIFT) + 1; in clock_get_pll6()
314 int k = ((rval & CCM_PLL6_CTRL_K_MASK) >> CCM_PLL6_CTRL_K_SHIFT) + 1; in clock_get_pll6()
322 uint32_t rval = readl(&ccm->mipi_pll_cfg); in clock_get_mipi_pll() local
323 unsigned int n = ((rval & CCM_MIPI_PLL_CTRL_N_MASK) >> CCM_MIPI_PLL_CTRL_N_SHIFT) + 1; in clock_get_mipi_pll()
324 unsigned int k = ((rval & CCM_MIPI_PLL_CTRL_K_MASK) >> CCM_MIPI_PLL_CTRL_K_SHIFT) + 1; in clock_get_mipi_pll()
325 unsigned int m = ((rval & CCM_MIPI_PLL_CTRL_M_MASK) >> CCM_MIPI_PLL_CTRL_M_SHIFT) + 1; in clock_get_mipi_pll()
H A Dclock_sun8i_a83t.c129 uint32_t rval = readl(&ccm->pll6_cfg); in clock_get_pll6() local
130 int n = ((rval & CCM_PLL6_CTRL_N_MASK) >> CCM_PLL6_CTRL_N_SHIFT); in clock_get_pll6()
131 int div1 = ((rval & CCM_PLL6_CTRL_DIV1_MASK) >> in clock_get_pll6()
133 int div2 = ((rval & CCM_PLL6_CTRL_DIV2_MASK) >> in clock_get_pll6()
H A Dclock_sun9i.c203 uint32_t rval = readl(&ccm->pll4_periph0_cfg); in clock_get_pll4_periph0() local
204 int n = ((rval & CCM_PLL4_CTRL_N_MASK) >> CCM_PLL4_CTRL_N_SHIFT); in clock_get_pll4_periph0()
205 int p = ((rval & CCM_PLL4_CTRL_P_MASK) >> CCM_PLL4_CTRL_P_SHIFT); in clock_get_pll4_periph0()
206 int m = ((rval & CCM_PLL4_CTRL_M_MASK) >> CCM_PLL4_CTRL_M_SHIFT) + 1; in clock_get_pll4_periph0()
H A Ddram_sun8i_a83t.c266 u32 i, rval; in mctl_channel_init() local
290 rval = 0x0; in mctl_channel_init()
292 rval = 0x2; in mctl_channel_init()
296 rval << 24); in mctl_channel_init()
298 rval << 24); in mctl_channel_init()
300 rval << 24); in mctl_channel_init()
302 rval << 24); in mctl_channel_init()
/rk3399_rockchip-uboot/drivers/mtd/
H A Dmtd_blk.c189 int rval; in mtd_map_read() local
225 rval = mtd_read(mtd, mapped_offset, read_length, &read_length, in mtd_map_read()
227 if (rval && rval != -EUCLEAN) { in mtd_map_read()
229 (u32)offset, rval); in mtd_map_read()
231 return rval; in mtd_map_read()
246 int rval = 0, blocksize; in mtd_map_write() local
303 rval = mtd_erase(mtd, &ei); in mtd_map_write()
304 if (rval) { in mtd_map_write()
305 pr_info("error %d while erasing %llx\n", rval, in mtd_map_write()
307 return rval; in mtd_map_write()
[all …]
/rk3399_rockchip-uboot/drivers/mmc/
H A Dsunxi_mmc.c209 unsigned rval = readl(&priv->reg->clkcr); in mmc_config_clock() local
212 rval &= ~SUNXI_MMC_CLK_ENABLE; in mmc_config_clock()
213 writel(rval, &priv->reg->clkcr); in mmc_config_clock()
222 rval &= ~SUNXI_MMC_CLK_DIVIDER_MASK; in mmc_config_clock()
223 writel(rval, &priv->reg->clkcr); in mmc_config_clock()
226 rval |= SUNXI_MMC_CLK_ENABLE; in mmc_config_clock()
227 writel(rval, &priv->reg->clkcr); in mmc_config_clock()
/rk3399_rockchip-uboot/drivers/phy/marvell/
H A Dcomphy_a3700.c112 u32 rval = 0xDEAD; in comphy_poll_reg() local
116 rval = readw(addr); /* 16 bit */ in comphy_poll_reg()
118 rval = readl(addr) ; /* 32 bit */ in comphy_poll_reg()
120 if ((rval & mask) == val) in comphy_poll_reg()
126 debug("Time out waiting (%p = %#010x)\n", addr, rval); in comphy_poll_reg()
/rk3399_rockchip-uboot/arch/powerpc/include/asm/
H A Dprocessor.h1142 #define mfdcr(rn) ({unsigned int rval; \
1144 : "=r" (rval)); rval;})
1147 #define mfmsr() ({unsigned int rval; \
1148 asm volatile("mfmsr %0" : "=r" (rval)); rval;})
1151 #define mfspr(rn) ({unsigned int rval; \
1153 : "=r" (rval)); rval;})
/rk3399_rockchip-uboot/drivers/ddr/altera/
H A Dsdram.c246 u32 rval; in sdram_write_verify() local
252 rval = readl(addr); in sdram_write_verify()
253 if (rval != val) { in sdram_write_verify()
255 addr, val, rval); in sdram_write_verify()
/rk3399_rockchip-uboot/arch/arm/mach-socfpga/
H A Dclock_manager_arria10.c884 int rval; in cm_basic_init() local
891 rval = of_get_clk_cfg(blob, &main_cfg, &per_cfg, &altrgrp_cfg); in cm_basic_init()
892 if (rval) in cm_basic_init()
893 return rval; in cm_basic_init()
895 rval = cm_full_cfg(&main_cfg, &per_cfg); in cm_basic_init()
906 return rval; in cm_basic_init()
/rk3399_rockchip-uboot/scripts/kconfig/
H A Dexpr.c922 union string_value lval = {}, rval = {}; in expr_calc_value() local
962 k2 = expr_parse_string(str2, e->right.sym->type, &rval); in expr_calc_value()
974 res = (lval.u > rval.u) - (lval.u < rval.u); in expr_calc_value()
976 res = (lval.s > rval.s) - (lval.s < rval.s); in expr_calc_value()
/rk3399_rockchip-uboot/common/
H A Ddlmalloc.c72 BOOL rval; in gcleanup() local
76 rval = VirtualFree ((void*)gAddressBase, in gcleanup()
79 assert (rval); in gcleanup()
84 rval = VirtualFree (head->base, 0, MEM_RELEASE); in gcleanup()
85 assert (rval); in gcleanup()
H A Ddlmalloc.src987 BOOL rval;
991 rval = VirtualFree ((void*)gAddressBase,
994 assert (rval);
999 rval = VirtualFree (head->base, 0, MEM_RELEASE);
1000 assert (rval);