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Searched refs:regval (Results 1 – 19 of 19) sorted by relevance

/rk3399_rockchip-uboot/arch/arm/mach-omap2/omap3/
H A Demif4.c66 unsigned int regval; in do_emif4_init() local
68 regval = (EMIF4_DDR1_READ_LAT | EMIF4_DDR1_PWRDN_DIS | in do_emif4_init()
70 writel(regval, &emif4_base->ddr_phyctrl1); in do_emif4_init()
71 writel(regval, &emif4_base->ddr_phyctrl1_shdw); in do_emif4_init()
75 regval = readl(&emif4_base->sdram_iodft_tlgc); in do_emif4_init()
76 regval |= (1<<10); in do_emif4_init()
77 writel(regval, &emif4_base->sdram_iodft_tlgc); in do_emif4_init()
83 regval |= (1<<0); in do_emif4_init()
84 writel(regval, &emif4_base->sdram_iodft_tlgc); in do_emif4_init()
86 regval = (EMIF4_TIM1_T_WTR | EMIF4_TIM1_T_RRD | in do_emif4_init()
[all …]
/rk3399_rockchip-uboot/arch/arm/mach-at91/armv7/
H A Dclock.c156 u32 regval, status; in at91_enable_periph_generated_clk() local
171 regval = readl(&pmc->pcr); in at91_enable_periph_generated_clk()
172 regval &= ~AT91_PMC_PCR_GCKCSS; in at91_enable_periph_generated_clk()
173 regval &= ~AT91_PMC_PCR_GCKDIV; in at91_enable_periph_generated_clk()
177 regval |= AT91_PMC_PCR_GCKCSS_SLOW_CLK; in at91_enable_periph_generated_clk()
180 regval |= AT91_PMC_PCR_GCKCSS_MAIN_CLK; in at91_enable_periph_generated_clk()
183 regval |= AT91_PMC_PCR_GCKCSS_PLLA_CLK; in at91_enable_periph_generated_clk()
186 regval |= AT91_PMC_PCR_GCKCSS_UPLL_CLK; in at91_enable_periph_generated_clk()
189 regval |= AT91_PMC_PCR_GCKCSS_MCK_CLK; in at91_enable_periph_generated_clk()
192 regval |= AT91_PMC_PCR_GCKCSS_AUDIO_CLK; in at91_enable_periph_generated_clk()
[all …]
/rk3399_rockchip-uboot/board/keymile/km_arm/
H A Dfpga_config.c37 u8 regval; in boco_clear_bits() local
40 ret = i2c_read(BOCO_ADDR, reg, 1, &regval, 1); in boco_clear_bits()
46 regval &= ~flags; in boco_clear_bits()
47 ret = i2c_write(BOCO_ADDR, reg, 1, &regval, 1); in boco_clear_bits()
60 u8 regval; in boco_set_bits() local
63 ret = i2c_read(BOCO_ADDR, reg, 1, &regval, 1); in boco_set_bits()
69 regval |= flags; in boco_set_bits()
70 ret = i2c_write(BOCO_ADDR, reg, 1, &regval, 1); in boco_set_bits()
89 u8 regval; in fpga_done() local
95 ret = i2c_read(BOCO_ADDR, SPI_REG, 1, &regval, 1); in fpga_done()
[all …]
/rk3399_rockchip-uboot/cmd/
H A Dmii.c123 ushort regval,
130 ushort regval);
147 ushort regval, in dump_reg() argument
156 prd->regno, regval, prd->name); in dump_reg()
165 regval & mask_in_place, in dump_reg()
168 if (special_field(prd->regno, pdesc, regval)) { in dump_reg()
176 (regval & mask_in_place) >> pdesc->lo, in dump_reg()
197 ushort regval) in special_field() argument
200 ushort speed_bits = regval & (BMCR_SPEED1000 | BMCR_SPEED100); in special_field()
203 (regval >> 6) & 1, in special_field()
[all …]
/rk3399_rockchip-uboot/arch/arm/mach-at91/
H A Dclock.c20 u32 regval; in at91_periph_clk_enable() local
30 regval = AT91_PMC_PCR_EN | AT91_PMC_PCR_CMD_WRITE | id | div_value; in at91_periph_clk_enable()
32 writel(regval, &pmc->pcr); in at91_periph_clk_enable()
43 u32 regval; in at91_periph_clk_disable() local
48 regval = AT91_PMC_PCR_CMD_WRITE | id; in at91_periph_clk_disable()
50 writel(regval, &pmc->pcr); in at91_periph_clk_disable()
/rk3399_rockchip-uboot/arch/mips/mach-ath79/ar934x/
H A Dclk.c229 static u32 ar934x_cpupll_to_hz(const u32 regval) in ar934x_cpupll_to_hz() argument
231 const u32 outdiv = (regval >> AR934X_PLL_CPU_CONFIG_OUTDIV_SHIFT) & in ar934x_cpupll_to_hz()
233 const u32 refdiv = (regval >> AR934X_PLL_CPU_CONFIG_REFDIV_SHIFT) & in ar934x_cpupll_to_hz()
235 const u32 nint = (regval >> AR934X_PLL_CPU_CONFIG_NINT_SHIFT) & in ar934x_cpupll_to_hz()
237 const u32 nfrac = (regval >> AR934X_PLL_CPU_CONFIG_NFRAC_SHIFT) & in ar934x_cpupll_to_hz()
244 static u32 ar934x_ddrpll_to_hz(const u32 regval) in ar934x_ddrpll_to_hz() argument
246 const u32 outdiv = (regval >> AR934X_PLL_DDR_CONFIG_OUTDIV_SHIFT) & in ar934x_ddrpll_to_hz()
248 const u32 refdiv = (regval >> AR934X_PLL_DDR_CONFIG_REFDIV_SHIFT) & in ar934x_ddrpll_to_hz()
250 const u32 nint = (regval >> AR934X_PLL_DDR_CONFIG_NINT_SHIFT) & in ar934x_ddrpll_to_hz()
252 const u32 nfrac = (regval >> AR934X_PLL_DDR_CONFIG_NFRAC_SHIFT) & in ar934x_ddrpll_to_hz()
/rk3399_rockchip-uboot/arch/arm/mach-mvebu/armada3700/
H A Dcpu.c72 u32 regval; in get_ref_clk() local
74 regval = (readl(MVEBU_TEST_PIN_LATCH_N) & MVEBU_XTAL_MODE_MASK) >> in get_ref_clk()
77 if (regval == MVEBU_XTAL_CLOCK_25MHZ) in get_ref_clk()
/rk3399_rockchip-uboot/drivers/net/phy/
H A Datheros.c57 int regval; in ar8035_config() local
62 regval = phy_read(phydev, MDIO_DEVAD_NONE, 0xe); in ar8035_config()
63 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, (regval|0x0018)); in ar8035_config()
66 regval = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e); in ar8035_config()
67 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, (regval|0x0100)); in ar8035_config()
H A Dmicrel_ksz90x1.c117 u16 regval = 0; in ksz90x1_of_config_group() local
127 regval |= ofcfg->grp[i].dflt << offset; in ksz90x1_of_config_group()
133 regval |= max << offset; in ksz90x1_of_config_group()
135 regval |= (val[i] / ps_to_regval) << offset; in ksz90x1_of_config_group()
143 return drv->writeext(phydev, 0, ofcfg->devad, ofcfg->reg, regval); in ksz90x1_of_config_group()
/rk3399_rockchip-uboot/arch/arm/mach-omap2/am33xx/
H A Dboard.c297 u32 regval; in uart_soft_reset() local
299 regval = readl(&uart_base->uartsyscfg); in uart_soft_reset()
300 regval |= UART_RESET; in uart_soft_reset()
301 writel(regval, &uart_base->uartsyscfg); in uart_soft_reset()
307 regval = readl(&uart_base->uartsyscfg); in uart_soft_reset()
308 regval |= UART_SMART_IDLE_EN; in uart_soft_reset()
309 writel(regval, &uart_base->uartsyscfg); in uart_soft_reset()
/rk3399_rockchip-uboot/drivers/sound/
H A Dmax98095.c146 u8 regval; in max98095_hw_params() local
177 if (rate_value(rate, &regval)) { in max98095_hw_params()
185 M98095_CLKMODE_MASK, regval); in max98095_hw_params()
257 u8 regval = 0; in max98095_set_fmt() local
291 regval |= M98095_DAI_MAS; in max98095_set_fmt()
302 regval |= M98095_DAI_DLY; in max98095_set_fmt()
315 regval |= M98095_DAI_WCI; in max98095_set_fmt()
318 regval |= M98095_DAI_BCI; in max98095_set_fmt()
321 regval |= M98095_DAI_BCI | M98095_DAI_WCI; in max98095_set_fmt()
331 regval); in max98095_set_fmt()
/rk3399_rockchip-uboot/board/Arcturus/ucp1020/
H A Ducp1020.c151 int regval; in board_phy_config() local
158 regval = in board_phy_config()
173 printf("0x%x", (regval & 0x1f)); in board_phy_config()
184 regval = ksz9031_phy_extended_read(phydev, 2, 0x01, 0x4000); in board_phy_config()
185 if (regval >= 0) in board_phy_config()
186 printf(" (ADDR 0x%x) ", regval & 0x1f); in board_phy_config()
/rk3399_rockchip-uboot/drivers/net/
H A Dsmc91111.c785 word regval;
789 regval = SMC_inw( dev, reg );
791 regval |= bit;
793 regval &= ~bit;
795 SMC_outw( dev, regval, 0 );
796 return(regval);
/rk3399_rockchip-uboot/drivers/mtd/nand/raw/
H A Darasan_nfc.c1136 u32 regval, eccpos_start, i, eccaddr; in arasan_nand_ecc_init() local
1158 regval = eccaddr | in arasan_nand_ecc_init()
1161 writel(regval, &arasan_nand_base->ecc_reg); in arasan_nand_ecc_init()
1164 regval = readl(&arasan_nand_base->memadr_reg2); in arasan_nand_ecc_init()
1165 regval &= ~ARASAN_NAND_MEM_ADDR2_BCH_MASK; in arasan_nand_ecc_init()
1166 regval |= (ecc_matrix[found].bchval << in arasan_nand_ecc_init()
1168 writel(regval, &arasan_nand_base->memadr_reg2); in arasan_nand_ecc_init()
/rk3399_rockchip-uboot/drivers/usb/eth/
H A Dlan7x.h165 int regval);
H A Dlan7x.c93 void lan7x_mdio_write(struct usb_device *udev, int phy_id, int idx, int regval) in lan7x_mdio_write() argument
103 lan7x_write_reg(udev, MII_DATA, regval); in lan7x_mdio_write()
H A Dsmsc95xx.c244 int regval) in smsc95xx_mdio_write() argument
254 val = regval; in smsc95xx_mdio_write()
/rk3399_rockchip-uboot/drivers/usb/gadget/
H A Datmel_usba_udc.c599 u32 regval; in set_address() local
602 regval = usba_readl(udc, CTRL); in set_address()
603 regval = USBA_BFINS(DEV_ADDR, addr, regval); in set_address()
604 usba_writel(udc, CTRL, regval); in set_address()
/rk3399_rockchip-uboot/drivers/pinctrl/
H A Dpinctrl-rockchip.c2588 int regval = ret; in rockchip_set_drive_perpin() local
2591 data |= ((regval & 0x3) << bit); in rockchip_set_drive_perpin()
2598 data = BIT(bit + 16) | (((regval > 3) ? 1 : 0) << bit); in rockchip_set_drive_perpin()