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Searched refs:reg5 (Results 1 – 6 of 6) sorted by relevance

/rk3399_rockchip-uboot/board/freescale/ls1043ardb/
H A Dcpld.c33 u8 reg5 = (u8)(reg >> 1); in cpld_set_altbank() local
37 cpld_rev_bit(&reg5); in cpld_set_altbank()
41 CPLD_WRITE(cfg_rcw_src1, reg5); in cpld_set_altbank()
55 u8 reg5 = (u8)(reg >> 1); in cpld_set_defbank() local
58 cpld_rev_bit(&reg5); in cpld_set_defbank()
62 CPLD_WRITE(cfg_rcw_src1, reg5); in cpld_set_defbank()
73 u8 reg5 = (u8)(reg >> 1); in cpld_set_nand() local
76 cpld_rev_bit(&reg5); in cpld_set_nand()
80 CPLD_WRITE(cfg_rcw_src1, reg5); in cpld_set_nand()
89 u8 reg5 = (u8)(reg >> 1); in cpld_set_sd() local
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/rk3399_rockchip-uboot/board/freescale/ls1046ardb/
H A Dcpld.c33 u8 reg5 = (u8)(reg >> 1); in cpld_set_altbank() local
37 cpld_rev_bit(&reg5); in cpld_set_altbank()
41 CPLD_WRITE(cfg_rcw_src1, reg5); in cpld_set_altbank()
55 u8 reg5 = (u8)(reg >> 1); in cpld_set_defbank() local
58 cpld_rev_bit(&reg5); in cpld_set_defbank()
62 CPLD_WRITE(cfg_rcw_src1, reg5); in cpld_set_defbank()
73 u8 reg5 = (u8)(reg >> 1); in cpld_set_sd() local
76 cpld_rev_bit(&reg5); in cpld_set_sd()
80 CPLD_WRITE(cfg_rcw_src1, reg5); in cpld_set_sd()
/rk3399_rockchip-uboot/board/freescale/ls2080aqds/
H A Dls2080aqds.c176 u8 reg5; in config_board_mux() local
178 reg5 = QIXIS_READ(brdcfg[5]); in config_board_mux()
182 reg5 = SET_SDHC_MUX_SEL(reg5, PIN_MUX_SEL_SDHC); in config_board_mux()
185 reg5 = SET_SDHC_MUX_SEL(reg5, PIN_MUX_SEL_DSPI); in config_board_mux()
192 QIXIS_WRITE(brdcfg[5], reg5); in config_board_mux()
/rk3399_rockchip-uboot/board/freescale/ls2080ardb/
H A Dls2080ardb.c184 u8 reg5; in config_board_mux() local
186 reg5 = QIXIS_READ(brdcfg[5]); in config_board_mux()
190 reg5 = SET_SDHC_MUX_SEL(reg5, PIN_MUX_SEL_SDHC); in config_board_mux()
193 reg5 = SET_SDHC_MUX_SEL(reg5, PIN_MUX_SEL_DSPI); in config_board_mux()
200 QIXIS_WRITE(brdcfg[5], reg5); in config_board_mux()
/rk3399_rockchip-uboot/board/freescale/p2041rdb/
H A Dcpld.c52 u8 reg5 = CPLD_READ(sw_ctl_on); in __cpld_set_altbank() local
54 CPLD_WRITE(sw_ctl_on, reg5 | CPLD_SWITCH_BANK_ENABLE); in __cpld_set_altbank()
/rk3399_rockchip-uboot/arch/arm/lib/
H A Dmemcpy.S27 .macro ldr8w ptr reg1 reg2 reg3 reg4 reg5 reg6 reg7 reg8 abort
28 ldmia \ptr!, {\reg1, \reg2, \reg3, \reg4, \reg5, \reg6, \reg7, \reg8}
39 .macro str8w ptr reg1 reg2 reg3 reg4 reg5 reg6 reg7 reg8 abort
40 stmia \ptr!, {\reg1, \reg2, \reg3, \reg4, \reg5, \reg6, \reg7, \reg8}