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Searched refs:readl (Results 1 – 25 of 960) sorted by relevance

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/rk3399_rockchip-uboot/arch/arm/cpu/pxa/
H A Dusb.c21 writel(readl(CKENA) | CKENA_2_USBHOST | CKENA_20_UDC, CKENA); in usb_cpu_init()
26 writel(readl(CKEN) | CKEN10_USBHOST, CKEN); in usb_cpu_init()
34 writel(readl(UHCHR) | UHCHR_FHR, UHCHR); in usb_cpu_init()
36 writel(readl(UHCHR) & ~UHCHR_FHR, UHCHR); in usb_cpu_init()
38 writel(readl(UHCHR) | UHCHR_FSBIR, UHCHR); in usb_cpu_init()
39 while (readl(UHCHR) & UHCHR_FSBIR) in usb_cpu_init()
43 writel(readl(UHCHR) & ~UHCHR_SSEP0, UHCHR); in usb_cpu_init()
46 writel(readl(UHCHR) & ~UHCHR_SSEP2, UHCHR); in usb_cpu_init()
48 writel(readl(UHCHR) & ~(UHCHR_SSEP1 | UHCHR_SSE), UHCHR); in usb_cpu_init()
55 writel(readl(UHCHR) | UHCHR_FHR, UHCHR); in usb_cpu_stop()
[all …]
/rk3399_rockchip-uboot/arch/arm/mach-uniphier/clk/
H A Dpll-ld4.c20 tmp = readl(SG_PINMON0); in upll_init()
25 tmp = readl(SC_UPLLCTRL); in upll_init()
60 tmp = readl(SG_PINMON0); in vpll_init()
64 tmp = readl(SC_VPLL27ACTRL); in vpll_init()
67 tmp = readl(SC_VPLL27BCTRL); in vpll_init()
72 tmp = readl(SC_VPLL27ACTRL3); in vpll_init()
75 tmp = readl(SC_VPLL27BCTRL3); in vpll_init()
80 tmp = readl(SC_VPLL27ACTRL2); in vpll_init()
83 tmp = readl(SC_VPLL27BCTRL2); in vpll_init()
88 tmp = readl(SC_VPLL27ACTRL2); in vpll_init()
[all …]
H A Dpll-pro4.c21 tmp = readl(SG_PINMON0); in vpll_init()
30 tmp = readl(SC_VPLL27ACTRL); in vpll_init()
33 tmp = readl(SC_VPLL27BCTRL); in vpll_init()
38 tmp = readl(SC_VPLL27ACTRL3); in vpll_init()
41 tmp = readl(SC_VPLL27BCTRL3); in vpll_init()
46 tmp = readl(SC_VPLL27ACTRL2); in vpll_init()
50 tmp = readl(SC_VPLL27BCTRL2); in vpll_init()
58 tmp = readl(SC_VPLL27ACTRL3); in vpll_init()
62 tmp = readl(SC_VPLL27BCTRL3); in vpll_init()
68 tmp = readl(SC_VPLL27ACTRL3); in vpll_init()
[all …]
H A Dclk-pxs2.c18 tmp = readl(SC_RSTCTRL); in uniphier_pxs2_clk_init()
29 readl(SC_RSTCTRL); /* dummy read */ in uniphier_pxs2_clk_init()
32 tmp = readl(SC_RSTCTRL2); in uniphier_pxs2_clk_init()
35 readl(SC_RSTCTRL2); /* dummy read */ in uniphier_pxs2_clk_init()
37 tmp = readl(SC_RSTCTRL6); in uniphier_pxs2_clk_init()
43 tmp = readl(SC_CLKCTRL); in uniphier_pxs2_clk_init()
55 readl(SC_CLKCTRL); /* dummy read */ in uniphier_pxs2_clk_init()
H A Dclk-pro5.c17 tmp = readl(SC_RSTCTRL); in uniphier_pro5_clk_init()
25 readl(SC_RSTCTRL); /* dummy read */ in uniphier_pro5_clk_init()
28 tmp = readl(SC_RSTCTRL2); in uniphier_pro5_clk_init()
31 readl(SC_RSTCTRL2); /* dummy read */ in uniphier_pro5_clk_init()
35 tmp = readl(SC_CLKCTRL); in uniphier_pro5_clk_init()
44 readl(SC_CLKCTRL); /* dummy read */ in uniphier_pro5_clk_init()
/rk3399_rockchip-uboot/arch/arm/cpu/armv7/stv0991/
H A Dpinmux.c21 writel((readl(&stv0991_creg->mux12) & GPIOC_31_MUX_MASK) | in stv0991_pinmux_config()
24 writel((readl(&stv0991_creg->mux12) & GPIOC_30_MUX_MASK) | in stv0991_pinmux_config()
28 writel((readl(&stv0991_creg->cfg_pad6) & GPIOC_31_MODE_MASK) | in stv0991_pinmux_config()
31 writel((readl(&stv0991_creg->cfg_pad6) & GPIOC_30_MODE_MASK) | in stv0991_pinmux_config()
37 writel((readl(&stv0991_creg->mux7) & GPIOB_17_MUX_MASK) | in stv0991_pinmux_config()
40 writel((readl(&stv0991_creg->mux7) & GPIOB_16_MUX_MASK) | in stv0991_pinmux_config()
45 writel(readl(&stv0991_creg->mux6) & 0x000000FF, in stv0991_pinmux_config()
49 writel(readl(&stv0991_creg->mux9) & 0xFFF00000, in stv0991_pinmux_config()
52 writel((readl(&stv0991_creg->vdd_pad1) & VDD_ETH_PS_MASK) | in stv0991_pinmux_config()
54 writel((readl(&stv0991_creg->vdd_pad1) & VDD_ETH_PS_MASK) | in stv0991_pinmux_config()
[all …]
/rk3399_rockchip-uboot/board/toradex/colibri_pxa270/
H A Dcolibri_pxa270.c66 writel((readl(UHCHR) | UHCHR_PCPL | UHCHR_PSPL) & in board_usb_init()
70 writel(readl(UHCHR) | UHCHR_FSBIR, UHCHR); in board_usb_init()
75 writel(readl(UHCHR) & ~UHCHR_SSE, UHCHR); in board_usb_init()
79 if (readl(PSSR) & PSSR_OTGPH) in board_usb_init()
80 writel(readl(PSSR) | PSSR_OTGPH, PSSR); in board_usb_init()
82 writel(readl(UHCRHDA) & ~(0x200), UHCRHDA); in board_usb_init()
83 writel(readl(UHCRHDA) | 0x100, UHCRHDA); in board_usb_init()
86 writel(readl(UHCRHDB) | (0x7<<17), UHCRHDB); in board_usb_init()
89 writel(readl(UP2OCR) | UP2OCR_HXOE | UP2OCR_HXS | in board_usb_init()
102 writel(readl(UHCHR) | UHCHR_FHR, UHCHR); in usb_board_stop()
[all …]
/rk3399_rockchip-uboot/arch/arm/cpu/arm926ejs/mx27/
H A Dgeneric.c49 if (readl(&pll->cscr) & CSCR_OSC26M_DIV1P5) { in clk_in_26m()
60 ulong cscr = readl(&pll->cscr); in imx_get_mpllclk()
68 return imx_decode_pll(readl(&pll->mpctl0), fref); in imx_get_mpllclk()
74 ulong cscr = readl(&pll->cscr); in imx_get_armclk()
89 ulong cscr = readl(&pll->cscr); in imx_get_ahbclk()
101 ulong cscr = readl(&pll->cscr); in imx_get_spllclk()
109 return imx_decode_pll(readl(&pll->spctl0), fref); in imx_get_spllclk()
121 return imx_decode_perclk((readl(&pll->pcdr1) & 0x3f) + 1); in imx_get_perclk1()
128 return imx_decode_perclk(((readl(&pll->pcdr1) >> 8) & 0x3f) + 1); in imx_get_perclk2()
135 return imx_decode_perclk(((readl(&pll->pcdr1) >> 16) & 0x3f) + 1); in imx_get_perclk3()
[all …]
/rk3399_rockchip-uboot/arch/arm/mach-exynos/
H A Dclock.c194 r = readl(&clk->apll_con0); in exynos4_get_pll_clk()
197 r = readl(&clk->mpll_con0); in exynos4_get_pll_clk()
200 r = readl(&clk->epll_con0); in exynos4_get_pll_clk()
201 k = readl(&clk->epll_con1); in exynos4_get_pll_clk()
204 r = readl(&clk->vpll_con0); in exynos4_get_pll_clk()
205 k = readl(&clk->vpll_con1); in exynos4_get_pll_clk()
224 r = readl(&clk->apll_con0); in exynos4x12_get_pll_clk()
227 r = readl(&clk->mpll_con0); in exynos4x12_get_pll_clk()
230 r = readl(&clk->epll_con0); in exynos4x12_get_pll_clk()
231 k = readl(&clk->epll_con1); in exynos4x12_get_pll_clk()
[all …]
/rk3399_rockchip-uboot/arch/arm/mach-omap2/am33xx/
H A Dclock_ti816x.c141 while (((readl(&cmdef->dmmclkctrl) >> 17) & 0x3) != 0) in enable_dmm_clocks()
153 while ((readl(&cmdef->l3fastclkstctrl) & 0x300) != 0x300) in enable_emif_clocks()
156 while (((readl(&cmdef->emif0clkctrl) >> 17) & 0x3) != 0) in enable_emif_clocks()
159 while (((readl(&cmdef->emif1clkctrl) >> 17) & 0x3) != 0) in enable_emif_clocks()
175 readl(CONTROL_STATUS); in ddr_delay()
183 main_pll_ctrl = readl(&cmpll->mainpll_ctrl); in main_pll_init_ti816x()
189 main_pll_ctrl = readl(&cmpll->mainpll_ctrl); in main_pll_init_ti816x()
195 main_pll_ctrl = readl(&cmpll->mainpll_ctrl); in main_pll_init_ti816x()
229 while ((readl(&cmpll->mainpll_ctrl) & BIT(7)) != BIT(7)) in main_pll_init_ti816x()
233 main_pll_ctrl = readl(&cmpll->mainpll_ctrl); in main_pll_init_ti816x()
[all …]
/rk3399_rockchip-uboot/drivers/watchdog/
H A Domap_wdt.c57 while ((readl(&wdt->wdtwwps)) & WDT_WWPS_PEND_WTGR) in hw_watchdog_reset()
64 while ((readl(&wdt->wdtwwps) & WDT_WWPS_PEND_WTGR)) in hw_watchdog_reset()
74 while (readl(&wdt->wdtwwps) & WDT_WWPS_PEND_WLDR) in omap_wdt_set_timeout()
78 while (readl(&wdt->wdtwwps) & WDT_WWPS_PEND_WLDR) in omap_wdt_set_timeout()
92 while (readl(&wdt->wdtwwps) != 0x0) in hw_watchdog_disable()
95 while (readl(&wdt->wdtwwps) != 0x0) in hw_watchdog_disable()
111 while (readl(&wdt->wdtwwps) & WDT_WWPS_PEND_WCLR) in hw_watchdog_init()
115 while (readl(&wdt->wdtwwps) & WDT_WWPS_PEND_WCLR) in hw_watchdog_init()
122 while ((readl(&wdt->wdtwwps)) & WDT_WWPS_PEND_WSPR) in hw_watchdog_init()
126 while ((readl(&wdt->wdtwwps)) & WDT_WWPS_PEND_WSPR) in hw_watchdog_init()
/rk3399_rockchip-uboot/arch/arm/cpu/armv7/bcm281xx/
H A Dclk-eth.c51 writel(readl(PLLE_POST_RESETB_ADDR) & in clk_eth_enable()
56 writel(readl(PLLE_RESETB_ADDR) | PLLE_RESETB_I_PLL_RESETB_PLLE_MASK, in clk_eth_enable()
63 if (readl(PLL_LOCK_ADDR) & PLL_LOCK_PLL_LOCK_PLLE_MASK) { in clk_eth_enable()
76 writel(readl(PLLE_POST_RESETB_ADDR) | in clk_eth_enable()
81 writel((readl(ESW_SYS_DIV_ADDR) & in clk_eth_enable()
86 writel(readl(ESW_SYS_DIV_ADDR) | ESW_SYS_DIV_TRIGGER_MASK, in clk_eth_enable()
94 if (!(readl(ESW_SYS_DIV_ADDR) & ESW_SYS_DIV_TRIGGER_MASK)) { in clk_eth_enable()
108 writel((readl(ESUB_AXI_DIV_DEBUG_ADDR) & in clk_eth_enable()
116 writel(readl(ESUB_AXI_DIV_DEBUG_ADDR) | in clk_eth_enable()
125 if (!(readl(ESUB_AXI_DIV_DEBUG_ADDR) & in clk_eth_enable()
/rk3399_rockchip-uboot/arch/arm/cpu/armv7/bcm235xx/
H A Dclk-eth.c51 writel(readl(PLLE_POST_RESETB_ADDR) & in clk_eth_enable()
56 writel(readl(PLLE_RESETB_ADDR) | PLLE_RESETB_I_PLL_RESETB_PLLE_MASK, in clk_eth_enable()
63 if (readl(PLL_LOCK_ADDR) & PLL_LOCK_PLL_LOCK_PLLE_MASK) { in clk_eth_enable()
76 writel(readl(PLLE_POST_RESETB_ADDR) | in clk_eth_enable()
81 writel((readl(ESW_SYS_DIV_ADDR) & in clk_eth_enable()
86 writel(readl(ESW_SYS_DIV_ADDR) | ESW_SYS_DIV_TRIGGER_MASK, in clk_eth_enable()
94 if (!(readl(ESW_SYS_DIV_ADDR) & ESW_SYS_DIV_TRIGGER_MASK)) { in clk_eth_enable()
108 writel((readl(ESUB_AXI_DIV_DEBUG_ADDR) & in clk_eth_enable()
116 writel(readl(ESUB_AXI_DIV_DEBUG_ADDR) | in clk_eth_enable()
125 if (!(readl(ESUB_AXI_DIV_DEBUG_ADDR) & in clk_eth_enable()
/rk3399_rockchip-uboot/drivers/usb/gadget/
H A Ddwc2_udc_otg_phy.c52 writel(readl(usb_phy_ctrl) | USB_PHY_CTRL_EN0, usb_phy_ctrl); in otg_phy_init()
55 writel((readl(&phy->phypwr) in otg_phy_init()
59 writel((readl(&phy->phypwr) &~(OTG_DISABLE_0 | ANALOG_PWRDOWN) in otg_phy_init()
63 writel((readl(&phy->phyclk) & ~(EXYNOS4X12_ID_PULLUP0 | in otg_phy_init()
67 writel((readl(&phy->phyclk) & ~(ID_PULLUP0 | COMMON_ON_N0)) | in otg_phy_init()
70 writel((readl(&phy->rstcon) &~(LINK_SW_RST | PHYLNK_SW_RST)) in otg_phy_init()
73 writel(readl(&phy->rstcon) in otg_phy_init()
87 writel(readl(&phy->phypwr) &~PHY_SW_RST0, &phy->rstcon); in otg_phy_off()
90 writel(readl(&phy->phypwr) | OTG_DISABLE_0 | ANALOG_PWRDOWN in otg_phy_off()
93 writel(readl(usb_phy_ctrl) &~USB_PHY_CTRL_EN0, usb_phy_ctrl); in otg_phy_off()
[all …]
H A Ddesignware_udc.c146 writel(readl(&inep_regs_p[ep_num].endp_cntl) | ENDP_CNTL_STALL, in udc_stall_ep()
149 writel(readl(&outep_regs_p[ep_num].endp_cntl) | ENDP_CNTL_STALL, in udc_stall_ep()
159 fifo_ptr += readl(&inep_regs_p[1].endp_bsorfn); in get_fifo()
163 fifo_ptr += readl(&inep_regs_p[0].endp_bsorfn); in get_fifo()
170 readl(&outep_regs_p[2].endp_maxpacksize) >> 16; in get_fifo()
177 fifo_ptr += readl(&outep_regs_p[0].endp_maxpacksize) >> 16; in get_fifo()
192 if (readl(&udc_regs_p->dev_stat) & DEV_STAT_RXFIFO_EMPTY) in usbgetpckfromfifo()
205 writel(readl(fifo_ptr), wrdp); in usbgetpckfromfifo()
215 readl(&outep_regs_p[epNum].write_done); in usbgetpckfromfifo()
384 u32 len = (readl(&outep_regs_p[0].endp_status) >> 11) & 0xfff; in dw_udc_ep0_rx()
[all …]
H A Dpxa27x_udc.c41 writel(readl(USIR1) | mask, USIR1); in udc_ack_int_UDCCR()
102 while (!(readl(UDCCSN(ep_num)) & UDCCSR_PC)) { in udc_write_urb()
151 if (readl(UDCCSN(ep_num)) & UDCCSR_BNE) in udc_read_urb()
152 n = readl(UDCBCN(ep_num)) & 0x3ff; in udc_read_urb()
158 data32[urb->actual_length / 4 + i / 4] = readl(UDCDN(ep_num)); in udc_read_urb()
178 n = readl(UDCBCR0); in udc_read_urb_ep0()
183 data32[ep0_urb->actual_length / 4 + i] = readl(UDCDN(0)); in udc_read_urb_ep0()
205 u32 udccsr0 = readl(UDCCSR0); in udc_handle_ep0()
225 udccsr0 = readl(UDCCSR0); in udc_handle_ep0()
235 if ((readl(UDCCSR0) & UDCCSR0_RNE) == 0) { in udc_handle_ep0()
[all …]
/rk3399_rockchip-uboot/arch/arm/cpu/arm926ejs/spear/
H A Dspear600.c35 ddr2v5 = readl(&misc_p->ddr_2v5_compensation); in sel_1v8()
40 ddr1v8 = readl(&misc_p->ddr_1v8_compensation); in sel_1v8()
45 while (!(readl(&misc_p->ddr_1v8_compensation) & DDR_COMP_ACCURATE)) in sel_1v8()
54 ddr1v8 = readl(&misc_p->ddr_1v8_compensation); in sel_2v5()
59 ddr2v5 = readl(&misc_p->ddr_2v5_compensation); in sel_2v5()
64 while (!(readl(&misc_p->ddr_2v5_compensation) & DDR_COMP_ACCURATE)) in sel_2v5()
78 ddrpad = readl(&misc_p->ddr_pad); in plat_ddr_init()
91 core3v3 = readl(&misc_p->core_3v3_compensation); in plat_ddr_init()
96 ddr1v8 = readl(&misc_p->ddr_1v8_compensation); in plat_ddr_init()
101 ddr2v5 = readl(&misc_p->ddr_2v5_compensation); in plat_ddr_init()
[all …]
/rk3399_rockchip-uboot/arch/arm/mach-omap2/omap5/
H A Dhwinit.c107 io_settings = (readl((*ctrl)->control_port_emif1_sdram_config) in io_settings_ddr3()
112 io_settings = (readl((*ctrl)->control_port_emif2_sdram_config) in io_settings_ddr3()
133 io_settings = readl((*ctrl)->control_smart1io_padconf_0) & in do_io_settings()
141 io_settings = readl((*ctrl)->control_smart1io_padconf_1) & in do_io_settings()
148 io_settings = readl((*ctrl)->control_smart1io_padconf_2) & in do_io_settings()
155 io_settings = readl((*ctrl)->control_smart2io_padconf_0) & in do_io_settings()
162 io_settings = readl((*ctrl)->control_smart2io_padconf_1) & in do_io_settings()
169 io_settings = readl((*ctrl)->control_smart2io_padconf_2) & in do_io_settings()
177 io_settings = readl((*ctrl)->control_smart3io_padconf_1) & in do_io_settings()
213 srcomp_value = readl((*ctrl)->control_srcomp_north_side + i*4); in srcomp_enable()
[all …]
/rk3399_rockchip-uboot/arch/arm/mach-imx/mx7ulp/
H A Dscg.c25 reg = readl(&scg1_regs->sosccsr); in scg_src_get_rate()
31 reg = readl(&scg1_regs->firccsr); in scg_src_get_rate()
37 reg = readl(&scg1_regs->sirccsr); in scg_src_get_rate()
43 reg = readl(&scg1_regs->rtccsr); in scg_src_get_rate()
77 reg = readl(&scg1_regs->sirccsr); in scg_sircdiv_get_rate()
81 reg = readl(&scg1_regs->sircdiv); in scg_sircdiv_get_rate()
115 reg = readl(&scg1_regs->firccsr); in scg_fircdiv_get_rate()
119 reg = readl(&scg1_regs->fircdiv); in scg_fircdiv_get_rate()
153 reg = readl(&scg1_regs->sosccsr); in scg_soscdiv_get_rate()
157 reg = readl(&scg1_regs->soscdiv); in scg_soscdiv_get_rate()
[all …]
/rk3399_rockchip-uboot/arch/arm/mach-at91/arm926ejs/
H A Deflash.c74 if ((readl(&dbu->cidr) & AT91_DBU_CID_ARCH_MASK) != AT91_DBU_CID_ARCH_9XExx) { in flash_init()
81 while ((readl(&eefc->fsr) & AT91_EEFC_FSR_FRDY) == 0) in flash_init()
83 id = readl(&eefc->frr); /* word 0 */ in flash_init()
84 size = readl(&eefc->frr); /* word 1 */ in flash_init()
85 pagesize = readl(&eefc->frr); /* word 2 */ in flash_init()
86 nplanes = readl(&eefc->frr); /* word 3 */ in flash_init()
87 planesize = readl(&eefc->frr); /* word 4 */ in flash_init()
91 tmp = readl(&eefc->frr); /* words 5..4+nplanes-1 */ in flash_init()
93 nlocks = readl(&eefc->frr); /* word 4+nplanes */ in flash_init()
108 tmp = readl(&eefc->frr); /* words 4+nplanes+1.. */ in flash_init()
[all …]
/rk3399_rockchip-uboot/cmd/
H A Darmflash.c51 val = readl((void *)start + i); in compute_crc()
91 foot1 = readl((void *)secend - 0x0c); in parse_bank()
98 afi->flash_mem_start = readl((void *)secend - 0x10); in parse_bank()
99 afi->flash_mem_end = readl((void *)secend - 0x14); in parse_bank()
100 afi->attributes = readl((void *)secend - 0x08); in parse_bank()
105 afi->regions[0].offset = readl((void *)imginfo + 0x04); in parse_bank()
107 readl((void *)imginfo + 0x08); in parse_bank()
108 afi->regions[0].size = readl((void *)imginfo + 0x0C); in parse_bank()
109 afi->entrypoint = readl((void *)imginfo + 0x10); in parse_bank()
115 foot1 = readl((void *)secend - 0x04); in parse_bank()
[all …]
/rk3399_rockchip-uboot/arch/arm/mach-tegra/tegra20/
H A Dwarmboot_avp.c51 if (readl(NV_PA_PG_UP_BASE + PG_UP_TAG_0) != PG_UP_TAG_AVP) in wb_start()
56 reg = readl(&clkrst->crc_rst_dev[TEGRA_DEV_U]); in wb_start()
62 osc_ctrl.word = readl(&clkrst->crc_osc_ctrl); in wb_start()
68 if (!(readl(&pmc->pmc_pwrgate_status) & PWRGATE_STATUS_CPU)) { in wb_start()
71 while (!(readl(&pmc->pmc_pwrgate_status) & PWRGATE_STATUS_CPU)) in wb_start()
76 reg = readl(&pmc->pmc_remove_clamping); in wb_start()
84 reg = readl(&clkrst->crc_rst_dev[TEGRA_DEV_L]); in wb_start()
100 reg = readl(&pmc->pmc_scratch41); in wb_start()
112 reg = readl(&clkrst->crc_clk_out_enb[TEGRA_DEV_L]); in wb_start()
117 reg = readl(TIMER_USEC_CNTR); in wb_start()
[all …]
/rk3399_rockchip-uboot/drivers/video/exynos/
H A Dexynos_mipi_dsi_lowlevel.c26 reg = readl(&mipi_dsim->swrst); in exynos_mipi_dsi_func_reset()
40 reg = readl(&mipi_dsim->swrst); in exynos_mipi_dsi_sw_reset()
52 unsigned int reg = readl(&mipi_dsim->intsrc); in exynos_mipi_dsi_sw_release()
64 unsigned int reg = readl(&mipi_dsim->intmsk); in exynos_mipi_dsi_set_interrupt_mask()
81 reg = readl(&mipi_dsim->fifoctrl); in exynos_mipi_dsi_init_fifo_pointer()
110 reg = (readl(&mipi_dsim->mdresol)) & ~(DSIM_MAIN_STAND_BY); in exynos_mipi_dsi_set_main_disp_resol()
128 reg = (readl(&mipi_dsim->mvporch)) & in exynos_mipi_dsi_set_main_disp_vporch()
146 reg = (readl(&mipi_dsim->mhporch)) & in exynos_mipi_dsi_set_main_disp_hporch()
161 reg = (readl(&mipi_dsim->msync)) & in exynos_mipi_dsi_set_main_disp_sync_area()
177 reg = (readl(&mipi_dsim->sdresol)) & in exynos_mipi_dsi_set_sub_disp_resol()
[all …]
/rk3399_rockchip-uboot/arch/arm/mach-omap2/omap4/
H A Dhwinit.c78 if (!(readl((*ctrl)->control_std_fuse_opp_bgap) & 0xFFFF)) { in do_io_settings()
95 if (!readl((*ctrl)->control_efuse_1)) in do_io_settings()
98 if ((omap4_rev < OMAP4460_ES1_0) || !readl((*ctrl)->control_efuse_2)) in do_io_settings()
122 switch (readl(CONTROL_ID_CODE)) { in init_omap_revision()
141 switch (readl(CONTROL_ID_CODE)) { in init_omap_revision()
162 die_id[0] = readl((*ctrl)->control_std_fuse_die_id_0); in omap_die_id()
163 die_id[1] = readl((*ctrl)->control_std_fuse_die_id_1); in omap_die_id()
164 die_id[2] = readl((*ctrl)->control_std_fuse_die_id_2); in omap_die_id()
165 die_id[3] = readl((*ctrl)->control_std_fuse_die_id_3); in omap_die_id()
184 value = readl((*ctrl)->control_pbiaslite); in vmmc_pbias_config()
[all …]
/rk3399_rockchip-uboot/arch/arm/cpu/arm926ejs/lpc32xx/
H A Dclk.c17 if (readl(&clk->sysclk_ctrl) & CLK_SYSCLK_PLL397) in get_sys_clk_rate()
39 val = readl(&clk->hclkpll_ctrl); in get_hclk_pll_rate()
74 val = readl(&clk->hclkdiv_ctrl) & CLK_HCLK_ARM_PLL_DIV_MASK; in get_hclk_clk_div()
88 val = readl(&clk->hclkdiv_ctrl) & CLK_HCLK_PERIPH_DIV_MASK; in get_periph_clk_div()
95 if (!(readl(&clk->pwr_ctrl) & CLK_PWR_NORMAL_RUN)) in get_periph_clk_rate()
105 if (!(readl(&clk->pwr_ctrl) & CLK_PWR_NORMAL_RUN)) in get_sdram_clk_rate()
110 if (readl(&clk->sdramclk_ctrl) & CLK_SDRAM_DDR_SEL) { in get_sdram_clk_rate()
112 switch (readl(&clk->hclkdiv_ctrl) & CLK_HCLK_DDRAM_MASK) { in get_sdram_clk_rate()
122 switch (readl(&clk->hclkdiv_ctrl) & CLK_HCLK_ARM_PLL_DIV_MASK) { in get_sdram_clk_rate()

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