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Searched refs:ratio (Results 1 – 24 of 24) sorted by relevance

/rk3399_rockchip-uboot/arch/arm/mach-exynos/
H A Dclock.c642 unsigned int ratio; in exynos4_get_pwm_clk() local
665 ratio = readl(&clk->div_peril3); in exynos4_get_pwm_clk()
666 ratio = ratio & 0xf; in exynos4_get_pwm_clk()
669 ratio = 8; in exynos4_get_pwm_clk()
673 pclk = sclk / (ratio + 1); in exynos4_get_pwm_clk()
682 unsigned int ratio; in exynos4x12_get_pwm_clk() local
685 ratio = 8; in exynos4x12_get_pwm_clk()
687 pclk = sclk / (ratio + 1); in exynos4x12_get_pwm_clk()
699 unsigned int ratio; in exynos4_get_uart_clk() local
731 ratio = readl(&clk->div_peril0); in exynos4_get_uart_clk()
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/rk3399_rockchip-uboot/arch/arm/cpu/armv7/ls102xa/
H A Dclock.c40 uint ratio[CONFIG_SYS_FSL_NUM_CC_PLLS]; in get_sys_info() local
56 ratio[i] = (in_be32(&clk->pllcgsr[i].pllcngsr) >> 1) & 0x3f; in get_sys_info()
57 if (ratio[i] > 4) in get_sys_info()
58 freq_c_pll[i] = sysclk * ratio[i]; in get_sys_info()
60 freq_c_pll[i] = sys_info->freq_systembus * ratio[i]; in get_sys_info()
/rk3399_rockchip-uboot/board/freescale/mpc8610hpcd/
H A DREADME50 pixis_reset altbank cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>
51 pixis_reset cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>
65 * 40 is SYSCLK, 2.5 is COREPLL ratio, 10 is MPXPLL ratio
/rk3399_rockchip-uboot/arch/x86/include/asm/
H A Dspeedstep.h29 uint8_t ratio:6; member
55 ((uint16_t)(state).ratio << SPEEDSTEP_RATIO_SHIFT) | \
58 ((uint8_t)(state).ratio * 2) + (state).nonint)
/rk3399_rockchip-uboot/arch/arm/cpu/armv8/fsl-layerscape/
H A Dfsl_lsch2_speed.c49 uint ratio[CONFIG_SYS_FSL_NUM_CC_PLLS]; in get_sys_info() local
79 ratio[i] = (in_be32(&clk->pllcgsr[i].pllcngsr) >> 1) & 0xff; in get_sys_info()
80 if (ratio[i] > 4) in get_sys_info()
81 freq_c_pll[i] = cluster_clk * ratio[i]; in get_sys_info()
83 freq_c_pll[i] = sys_info->freq_systembus * ratio[i]; in get_sys_info()
H A Dfsl_lsch3_speed.c68 uint ratio[CONFIG_SYS_FSL_NUM_CC_PLLS]; in get_sys_info() local
112 ratio[i] = (in_le32(offset) >> 1) & 0x3f; in get_sys_info()
113 freq_c_pll[i] = sysclk * ratio[i]; in get_sys_info()
/rk3399_rockchip-uboot/drivers/timer/
H A Dtsc_timer.c85 u32 lo, hi, ratio, freq_id, freq; in cpu_mhz_from_msr() local
98 ratio = (lo >> 8) & 0xff; in cpu_mhz_from_msr()
101 ratio = (hi >> 8) & 0x1f; in cpu_mhz_from_msr()
103 debug("Maximum core-clock to bus-clock ratio: 0x%x\n", ratio); in cpu_mhz_from_msr()
119 res = freq * ratio / 1000; in cpu_mhz_from_msr()
/rk3399_rockchip-uboot/board/freescale/mpc8544ds/
H A DREADME68 pixis_reset altbank cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>
69 pixis_reset cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>
83 * 40 is SYSCLK, 2.5 is COREPLL ratio, 10 is MPXPLL ratio
/rk3399_rockchip-uboot/board/freescale/mpc8641hpcn/
H A DREADME167 pixis_reset altbank cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>
168 pixis_reset cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>
182 * 40 is SYSCLK, 2.5 is COREPLL ratio, 10 is MPXPLL ratio
/rk3399_rockchip-uboot/drivers/fpga/
H A Dsocfpga_gen5.c25 static void fpgamgr_set_cd_ratio(unsigned long ratio) in fpgamgr_set_cd_ratio() argument
29 (ratio & 0x3) << FPGAMGRREGS_CTRL_CDRATIO_LSB); in fpgamgr_set_cd_ratio()
H A Dsocfpga_arria10.c34 static void fpgamgr_set_cd_ratio(unsigned long ratio);
131 static void fpgamgr_set_cd_ratio(unsigned long ratio) in fpgamgr_set_cd_ratio() argument
137 (ratio << ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_LSB) & in fpgamgr_set_cd_ratio()
/rk3399_rockchip-uboot/board/freescale/mpc8572ds/
H A DREADME62 pixis_reset altbank cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>
63 pixis_reset cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>
/rk3399_rockchip-uboot/arch/powerpc/cpu/mpc85xx/
H A Dspeed.c76 uint ratio[CONFIG_SYS_FSL_NUM_CC_PLLS]; in get_sys_info() local
155 ratio[i] = (in_be32(&clk->pllcgsr[i].pllcngsr) >> 1) & 0x3f; in get_sys_info()
156 if (ratio[i] > 4) in get_sys_info()
157 freq_c_pll[i] = sysclk * ratio[i]; in get_sys_info()
159 freq_c_pll[i] = sys_info->freq_systembus * ratio[i]; in get_sys_info()
/rk3399_rockchip-uboot/lib/lzma/
H A Dlzma.txt9 compression ratio and very fast decompression.
12 It was improved in way of maximum increasing of compression ratio,
197 Usually big number gives a little bit better compression ratio
215 ratio, but they often works pretty fast in combination with
255 Compression ratio hints
261 To increase the compression ratio for LZMA compressing it's desirable
270 You can increase the compression ratio for some data types, using
272 increase the compression ratio on 5-10% for code for those CPU ISAs:
277 You can check the compression ratio gain of these filters with such
292 since compression ratio with filtering is higher.
H A Dhistory.txt135 - Compression ratio was improved in -a2 mode
/rk3399_rockchip-uboot/drivers/video/drm/
H A Dsii902x.c347 u8 ratio; in sii902x_bridge_mode_set() local
414 ratio = SII902X_TPI_CLK_RATIO_2X; in sii902x_bridge_mode_set()
416 ratio = SII902X_TPI_CLK_RATIO_1X; in sii902x_bridge_mode_set()
418 SII902X_TPI_CLK_RATIO_MASK, ratio); in sii902x_bridge_mode_set()
/rk3399_rockchip-uboot/drivers/ddr/altera/
H A Dsequencer.c116 u32 ratio; in phy_mgr_initialize() local
139 ratio = rwcfg->mem_dq_per_read_dqs / in phy_mgr_initialize()
141 param->read_correct_mask_vg = (1 << ratio) - 1; in phy_mgr_initialize()
142 param->write_correct_mask_vg = (1 << ratio) - 1; in phy_mgr_initialize()
445 const int ratio = rwcfg->mem_if_read_dqs_width / in scc_mgr_set_oct_out1_delay() local
447 const int base = write_group * ratio; in scc_mgr_set_oct_out1_delay()
456 for (i = 0; i < ratio; i++) in scc_mgr_set_oct_out1_delay()
557 const int ratio = rwcfg->mem_if_read_dqs_width / in scc_mgr_load_dqs_for_write_group() local
559 const int base = write_group * ratio; in scc_mgr_load_dqs_for_write_group()
568 for (i = 0; i < ratio; i++) in scc_mgr_load_dqs_for_write_group()
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/rk3399_rockchip-uboot/doc/device-tree-bindings/exynos/
H A Ddwmmc.txt35 . DIVRATIO: Clock Divide ratio select.
/rk3399_rockchip-uboot/drivers/video/rockchip/
H A DKconfig68 16,18, 24 bits per pixel with upto 2k resolution ratio.
/rk3399_rockchip-uboot/doc/device-tree-bindings/video/
H A Dexynos-fb.txt56 samsung,sclk-div: parent_clock/source_clock ratio
/rk3399_rockchip-uboot/lib/
H A DKconfig229 ratio and fairly fast decompression speed. See also
238 ratio and fairly fast decompression speed. See also
/rk3399_rockchip-uboot/drivers/power/regulator/
H A DKconfig74 controlled by PWM duty ratio. Some of Rockchip board using this kind
/rk3399_rockchip-uboot/board/sbc8548/
H A DREADME37 to reflect a different CCB:SYSCLK ratio]
/rk3399_rockchip-uboot/
H A DREADME336 Defines the core time base clock divider ratio compared to the
338 devices it can be 16 or 32. The ratio varies from SoC to Soc.