| #
c83a824e |
| 04-Feb-2017 |
Tom Rini <trini@konsulko.com> |
Merge git://git.denx.de/u-boot-fsl-qoriq
Signed-off-by: Tom Rini <trini@konsulko.com>
Conflicts:
configs/ls1046aqds_defconfig
configs/ls1046aqds_nand_defconfig
configs/ls1046aqds_qspi_defconfig
Merge git://git.denx.de/u-boot-fsl-qoriq
Signed-off-by: Tom Rini <trini@konsulko.com>
Conflicts:
configs/ls1046aqds_defconfig
configs/ls1046aqds_nand_defconfig
configs/ls1046aqds_qspi_defconfig
configs/ls1046aqds_sdcard_ifc_defconfig
configs/ls1046aqds_sdcard_qspi_defconfig
configs/ls1046ardb_emmc_defconfig
configs/ls1046ardb_qspi_defconfig
configs/ls1046ardb_sdcard_defconfig
show more ...
|
| #
8e63ed51 |
| 02-Feb-2017 |
Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
arch: arm: update the IFC IP input clock
IFC IP clock is always a constant divisor of platform clock
pre-defined per SoC. Clock control register (CCR) used in
current implementation governs IFC IP o
arch: arm: update the IFC IP input clock
IFC IP clock is always a constant divisor of platform clock
pre-defined per SoC. Clock control register (CCR) used in
current implementation governs IFC IP output clock.
Update sys_info->freq_localbus to represent IFC input clock with
value constant divisor of platform clock.
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
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|
| #
b939689c |
| 05-May-2015 |
Albert ARIBAUD <albert.u.boot@aribaud.net> |
Merge branch 'u-boot/master' into 'u-boot-arm/master'
|
| #
3f6dcdb9 |
| 24-Apr-2015 |
Tom Rini <trini@konsulko.com> |
Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriq
|
| #
39b0bbbb |
| 21-Mar-2015 |
Jaiprakash Singh <b44839@freescale.com> |
driver/ifc: Add 64KB page support
IFC has two register pages.Till IFC version 1.4 each
register page is 4KB each.But IFC ver 2.0 register page
size is 64KB each.IFC regiters structure is break into
driver/ifc: Add 64KB page support
IFC has two register pages.Till IFC version 1.4 each
register page is 4KB each.But IFC ver 2.0 register page
size is 64KB each.IFC regiters structure is break into
two viz FCM and RUNTIME.FCM(Flash control machine) registers
are defined in PAGE0 and controls IFC generic functionality.
RUNTIME registers are defined in PAGE1 and controls NAND and
GPCM funcinality.
FCM and RUNTIME structures defination is common for IFC
version 1.4 and 2.0.
Signed-off-by: Jaiprakash Singh <b44839@freescale.com>
Signed-off-by: York Sun <yorksun@freescale.com>
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|
| #
42817eb8 |
| 22-Sep-2014 |
Stefano Babic <sbabic@denx.de> |
Merge branch 'master' of git://git.denx.de/u-boot-arm
|
| #
8c9c74e4 |
| 10-Sep-2014 |
Tom Rini <trini@ti.com> |
Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriq
|
| #
d60a2099 |
| 05-Sep-2014 |
Wang Huan <b18965@freescale.com> |
arm: ls102xa: Add Freescale LS102xA SoC support
The QorIQ LS1 family is built on Layerscape architecture,
the industry's first software-aware, core-agnostic networking
architecture to offer unpreced
arm: ls102xa: Add Freescale LS102xA SoC support
The QorIQ LS1 family is built on Layerscape architecture,
the industry's first software-aware, core-agnostic networking
architecture to offer unprecedented efficiency and scale.
Freescale LS102xA is a set of SoCs combines two ARM
Cortex-A7 cores that have been optimized for high
reliability and pack the highest level of integration
available for sub-3 W embedded communications processors
with Layerscape architecture and with a comprehensive
enablement model focused on ease of programmability.
Signed-off-by: Alison Wang <alison.wang@freescale.com>
Signed-off-by: Jason Jin <jason.jin@freescale.com>
Signed-off-by: Jingchang Lu <jingchang.lu@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
show more ...
|