| /rk3399_rockchip-uboot/doc/device-tree-bindings/pwm/ |
| H A D | pwm.txt | 8 with a property containing a 'pwm-list':
10 pwm-list ::= <single-pwm> [pwm-list]
11 single-pwm ::= <pwm-phandle> <pwm-specifier>
12 pwm-phandle : phandle to PWM controller node
13 pwm-specifier : array of #pwm-cells specifying the given PWM
18 An optional property "pwm-names" may contain a list of strings to label
19 each of the PWM devices listed in the "pwms" property. If no "pwm-names"
23 "pwm-names" property to map the name of the PWM device requested by the
29 pwm: pwm {
30 #pwm-cells = <2>;
[all …]
|
| H A D | tegra20-pwm.txt | 5 - "nvidia,tegra20-pwm"
6 - "nvidia,tegra30-pwm"
8 - #pwm-cells: On Tegra the number of cells used to specify a PWM is 2. The
14 pwm: pwm@7000a000 {
15 compatible = "nvidia,tegra20-pwm";
17 #pwm-cells = <2>;
|
| /rk3399_rockchip-uboot/drivers/pwm/ |
| H A D | pwm-imx.c | 19 struct pwm_regs *pwm = (struct pwm_regs *)pwm_id_to_reg(pwm_id); in pwm_init() local
21 if (!pwm) in pwm_init()
24 writel(0, &pwm->ir); in pwm_init()
30 struct pwm_regs *pwm = (struct pwm_regs *)pwm_id_to_reg(pwm_id); in pwm_config() local
34 if (!pwm) in pwm_config()
44 writel(cr, &pwm->cr); in pwm_config()
46 writel(duty_cycles, &pwm->sar); in pwm_config()
48 writel(period_cycles, &pwm->pr); in pwm_config()
54 struct pwm_regs *pwm = (struct pwm_regs *)pwm_id_to_reg(pwm_id); in pwm_enable() local
56 if (!pwm) in pwm_enable()
[all …]
|
| H A D | Makefile | 13 obj-$(CONFIG_DM_PWM) += pwm-uclass.o
16 obj-$(CONFIG_PWM_IMX) += pwm-imx.o pwm-imx-util.o
|
| /rk3399_rockchip-uboot/drivers/video/exynos/ |
| H A D | exynos_pwm_bl.c | 20 static struct pwm_backlight_data *pwm; variable
24 int brightness = pwm->brightness; in exynos_pwm_backlight_update_status()
25 int max = pwm->max_brightness; in exynos_pwm_backlight_update_status()
28 pwm_config(pwm->pwm_id, 0, pwm->period); in exynos_pwm_backlight_update_status()
29 pwm_disable(pwm->pwm_id); in exynos_pwm_backlight_update_status()
31 pwm_config(pwm->pwm_id, in exynos_pwm_backlight_update_status()
32 brightness * pwm->period / max, pwm->period); in exynos_pwm_backlight_update_status()
33 pwm_enable(pwm->pwm_id); in exynos_pwm_backlight_update_status()
40 pwm = pd; in exynos_pwm_backlight_init()
|
| /rk3399_rockchip-uboot/arch/arm/cpu/armv7/s5p-common/ |
| H A D | pwm.c | 18 const struct s5p_timer *pwm = in pwm_enable() local
22 tcon = readl(&pwm->tcon); in pwm_enable()
25 writel(tcon, &pwm->tcon); in pwm_enable()
32 const struct s5p_timer *pwm = in pwm_disable() local
36 tcon = readl(&pwm->tcon); in pwm_disable()
39 writel(tcon, &pwm->tcon); in pwm_disable()
61 const struct s5p_timer *pwm = in pwm_config() local
97 writel(tcnt, &pwm->tcntb0 + offset); in pwm_config()
98 writel(tcmp, &pwm->tcmpb0 + offset); in pwm_config()
101 tcon = readl(&pwm->tcon); in pwm_config()
[all …]
|
| /rk3399_rockchip-uboot/arch/arm/dts/ |
| H A D | rv1103b.dtsi | 323 pwm0_4ch_0: pwm@20550000 {
324 compatible = "rockchip,rv1103b-pwm", "rockchip,rk3576-pwm";
327 #pwm-cells = <3>;
331 clock-names = "pwm", "pclk";
335 pwm0_4ch_1: pwm@20551000 {
336 compatible = "rockchip,rv1103b-pwm", "rockchip,rk3576-pwm";
339 #pwm-cells = <3>;
343 clock-names = "pwm", "pclk";
347 pwm0_4ch_2: pwm@20552000 {
348 compatible = "rockchip,rv1103b-pwm", "rockchip,rk3576-pwm";
[all …]
|
| H A D | rv1106.dtsi | 356 rockchip,pwm-output-mode;
363 pwm0: pwm@ff350000 {
364 compatible = "rockchip,rv1106-pwm", "rockchip,rk3328-pwm";
366 #pwm-cells = <3>;
370 clock-names = "pwm", "pclk";
374 pwm1: pwm@ff350010 {
375 compatible = "rockchip,rv1106-pwm", "rockchip,rk3328-pwm";
377 #pwm-cells = <3>;
381 clock-names = "pwm", "pclk";
385 pwm2: pwm@ff350020 {
[all …]
|
| H A D | rv1126b.dtsi | 1249 pwm1_4ch_0: pwm@20700000 {
1250 compatible = "rockchip,rv1126b-pwm", "rockchip,rk3576-pwm";
1254 clock-names = "pwm", "pclk";
1257 #pwm-cells = <3>;
1261 pwm1_4ch_1: pwm@20710000 {
1262 compatible = "rockchip,rv1126b-pwm", "rockchip,rk3576-pwm";
1266 clock-names = "pwm", "pclk";
1269 #pwm-cells = <3>;
1273 pwm1_4ch_2: pwm@20720000 {
1274 compatible = "rockchip,rv1126b-pwm", "rockchip,rk3576-pwm";
[all …]
|
| H A D | tegra20-medcom-wide.dts | 43 pwm: pwm@7000a000 { label
59 nvidia,pwm = <&pwm 0 500000>;
|
| H A D | tegra20-tec.dts | 55 pwm: pwm@7000a000 { label
71 nvidia,pwm = <&pwm 0 500000>;
|
| H A D | rk3506.dtsi | 503 pwm1_8ch_0: pwm@ff170000 {
504 compatible = "rockchip,rk3506-pwm", "rockchip,rk3576-pwm";
508 clock-names = "pwm", "pclk";
509 #pwm-cells = <3>;
513 pwm1_8ch_1: pwm@ff171000 {
514 compatible = "rockchip,rk3506-pwm", "rockchip,rk3576-pwm";
518 clock-names = "pwm", "pclk";
519 #pwm-cells = <3>;
523 pwm1_8ch_2: pwm@ff172000 {
524 compatible = "rockchip,rk3506-pwm", "rockchip,rk3576-pwm";
[all …]
|
| H A D | rk1808.dtsi | 342 pwm0: pwm@ff3d0000 {
343 compatible = "rockchip,rk1808-pwm", "rockchip,rk3328-pwm";
345 #pwm-cells = <3>;
349 clock-names = "pwm", "pclk";
353 pwm1: pwm@ff3d0010 {
354 compatible = "rockchip,rk1808-pwm", "rockchip,rk3328-pwm";
356 #pwm-cells = <3>;
360 clock-names = "pwm", "pclk";
364 pwm2: pwm@ff3d0020 {
365 compatible = "rockchip,rk1808-pwm", "rockchip,rk3328-pwm";
[all …]
|
| H A D | rk3562.dtsi | 845 pwm0: pwm@ff230000 {
846 compatible = "rockchip,rk3562-pwm", "rockchip,rk3328-pwm";
848 #pwm-cells = <3>;
852 clock-names = "pwm", "pclk";
856 pwm1: pwm@ff230010 {
857 compatible = "rockchip,rk3562-pwm", "rockchip,rk3328-pwm";
859 #pwm-cells = <3>;
863 clock-names = "pwm", "pclk";
867 pwm2: pwm@ff230020 {
868 compatible = "rockchip,rk3562-pwm", "rockchip,rk3328-pwm";
[all …]
|
| H A D | rk3036.dtsi | 161 pwm0: pwm@20050000 {
162 compatible = "rockchip,rk2928-pwm";
164 #pwm-cells = <3>;
168 clock-names = "pwm";
172 pwm1: pwm@20050010 {
173 compatible = "rockchip,rk2928-pwm";
175 #pwm-cells = <3>;
179 clock-names = "pwm";
183 pwm2: pwm@20050020 {
184 compatible = "rockchip,rk2928-pwm";
[all …]
|
| H A D | exynos5250.dtsi | 119 pwm: pwm@12dd0000 { label
120 compatible = "samsung,exynos4210-pwm";
122 samsung,pwm-outputs = <0>, <1>, <2>, <3>;
123 #pwm-cells = <3>;
|
| H A D | imx6ul.dtsi | 334 pwm1: pwm@02080000 {
335 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
341 #pwm-cells = <2>;
345 pwm2: pwm@02084000 {
346 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
352 #pwm-cells = <2>;
356 pwm3: pwm@02088000 {
357 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
363 #pwm-cells = <2>;
367 pwm4: pwm@0208c000 {
[all …]
|
| H A D | rk3588s.dtsi | 561 pwm0: pwm@fd8b0000 {
562 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
564 #pwm-cells = <3>;
568 clock-names = "pwm", "pclk";
572 pwm1: pwm@fd8b0010 {
573 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
575 #pwm-cells = <3>;
579 clock-names = "pwm", "pclk";
583 pwm2: pwm@fd8b0020 {
584 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
[all …]
|
| H A D | exynos54xx.dtsi | 178 samsung,pwm-out-gpio = <&gpb2 0 GPIO_ACTIVE_HIGH>;
200 pwm: pwm@12dd0000 { label
201 compatible = "samsung,exynos4210-pwm";
203 samsung,pwm-outputs = <0>, <1>, <2>, <3>;
204 #pwm-cells = <3>;
|
| H A D | rv1126.dtsi | 763 pwm0: pwm@ff430000 {
764 compatible = "rockchip,rv1126-pwm", "rockchip,rk3328-pwm";
766 #pwm-cells = <3>;
770 clock-names = "pwm", "pclk";
774 pwm1: pwm@ff430010 {
775 compatible = "rockchip,rv1126-pwm", "rockchip,rk3328-pwm";
777 #pwm-cells = <3>;
781 clock-names = "pwm", "pclk";
785 pwm2: pwm@ff430020 {
786 compatible = "rockchip,rv1126-pwm", "rockchip,rk3328-pwm";
[all …]
|
| H A D | rk3xxx.dtsi | 277 pwm0: pwm@20030000 {
278 compatible = "rockchip,rk2928-pwm";
280 #pwm-cells = <2>;
285 pwm1: pwm@20030010 {
286 compatible = "rockchip,rk2928-pwm";
288 #pwm-cells = <2>;
301 pwm2: pwm@20050020 {
302 compatible = "rockchip,rk2928-pwm";
304 #pwm-cells = <2>;
309 pwm3: pwm@20050030 {
[all …]
|
| H A D | rk3568.dtsi | 610 pwm0: pwm@fdd70000 {
611 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
613 #pwm-cells = <3>;
617 clock-names = "pwm", "pclk";
621 pwm1: pwm@fdd70010 {
622 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
624 #pwm-cells = <3>;
628 clock-names = "pwm", "pclk";
632 pwm2: pwm@fdd70020 {
633 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
[all …]
|
| /rk3399_rockchip-uboot/drivers/video/ |
| H A D | pwm_backlight.c | 20 struct udevice *pwm; member
49 ret = pwm_set_invert(priv->pwm, priv->channel, priv->polarity); in pwm_backlight_enable()
57 ret = pwm_set_config(priv->pwm, priv->channel, priv->period_ns, in pwm_backlight_enable()
61 ret = pwm_set_enable(priv->pwm, priv->channel, true); in pwm_backlight_enable()
78 ret = pwm_set_config(priv->pwm, priv->channel, priv->period_ns, 0); in pwm_backlight_disable()
88 ret = pwm_set_enable(priv->pwm, priv->channel, false); in pwm_backlight_disable()
139 ret = uclass_get_device_by_ofnode(UCLASS_PWM, args.node, &priv->pwm); in pwm_backlight_ofdata_to_platdata()
|
| /rk3399_rockchip-uboot/doc/device-tree-bindings/video/ |
| H A D | tegra20-dc.txt | 25 - nvidia,pwm : pwm to use to set display contrast (see tegra20-pwm.txt)
30 * delay between backlight_vdd and pwm-rise
31 * delay between pwm-rise and backlight_en-rise
79 nvidia,pwm = <&pwm 2 0>;
|
| /rk3399_rockchip-uboot/drivers/power/regulator/ |
| H A D | pwm_regulator.c | 33 struct udevice *pwm; member
48 return pwm_set_enable(priv->pwm, priv->pwm_id, enable); in pwm_regulator_enable()
76 ret = pwm_set_invert(priv->pwm, priv->pwm_id, priv->polarity); in pwm_regulator_set_voltage()
82 ret = pwm_set_config(priv->pwm, priv->pwm_id, in pwm_regulator_set_voltage()
121 ret = uclass_get_device_by_ofnode(UCLASS_PWM, args.node, &priv->pwm); in pwm_regulator_ofdata_to_platdata()
|