Searched refs:pllm (Results 1 – 9 of 9) sorted by relevance
| /rk3399_rockchip-uboot/arch/arm/mach-davinci/ |
| H A D | cpu.c | 58 int pllm; in clk_get() local
81 pllm = readl(pll_base + PLLC_PLLM) + 1; in clk_get()
84 pll_out *= pllm; in clk_get()
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| H A D | dm365_lowlevel.c | 57 writel(pllmult, &dv_pll0_regs->pllm); in dm365_pll1_init()
103 int dm365_pll2_init(unsigned long pllm, unsigned long prediv) in dm365_pll2_init() argument
139 writel(pllm, &dv_pll1_regs->pllm); in dm365_pll2_init()
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| H A D | da850_lowlevel.c | 90 writel(pllmult, ®->pllm); in da850_pll_init()
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| /rk3399_rockchip-uboot/arch/arm/mach-davinci/include/mach/ |
| H A D | dm365_lowlevel.h | 18 int dm365_pll2_init(unsigned long pllm, unsigned long prediv);
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| H A D | pll_defs.h | 19 unsigned int pllm; /* 0x110 */ member
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| H A D | hardware.h | 401 dv_reg pllm; member
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| /rk3399_rockchip-uboot/arch/arm/mach-stm32/stm32f4/ |
| H A D | clock.c | 204 u16 pllm, plln, pllp; in clock_get() local
205 pllm = (readl(&STM32_RCC->pllcfgr) & RCC_PLLCFGR_PLLM_MASK); in clock_get()
210 sysclk = ((CONFIG_STM32_HSE_HZ / pllm) * plln) / pllp; in clock_get()
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| /rk3399_rockchip-uboot/arch/arm/mach-keystone/ |
| H A D | clock.c | 63 u32 pllm, plld, bwadj; in configure_mult_div() local
65 pllm = data->pll_m - 1; in configure_mult_div()
70 pllctl_reg_write(data->pll, mult, pllm & PLLM_MULT_LO_MASK); in configure_mult_div()
74 pllm << CFG_PLLCTL0_PLLM_SHIFT); in configure_mult_div()
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| /rk3399_rockchip-uboot/drivers/clk/ |
| H A D | clk_stm32f7.c | 190 u16 pllm, plln, pllp; in stm32_clk_get_rate() local
191 pllm = (readl(®s->pllcfgr) & RCC_PLLCFGR_PLLM_MASK); in stm32_clk_get_rate()
196 sysclk = ((CONFIG_STM32_HSE_HZ / pllm) * plln) / pllp; in stm32_clk_get_rate()
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