Searched refs:pll_config (Results 1 – 6 of 6) sorted by relevance
| /rk3399_rockchip-uboot/drivers/video/ |
| H A D | ssd2828.c | 278 static u32 decode_pll_config(u32 pll_config, u32 reference_freq_khz) in decode_pll_config() argument
280 u32 mul_factor = pll_config & 0xFF; in decode_pll_config()
281 u32 div_factor = (pll_config >> 8) & 0x1F; in decode_pll_config()
343 u32 lp_div, pll_freq_kbps, reference_freq_khz, pll_config; in ssd2828_init() local
405 pll_config = construct_pll_config( in ssd2828_init()
408 write_hw_register(cfg, SSD2828_PLCR, pll_config); in ssd2828_init()
410 pll_freq_kbps = decode_pll_config(pll_config, reference_freq_khz); in ssd2828_init()
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| /rk3399_rockchip-uboot/arch/arm/mach-omap2/am33xx/ |
| H A D | clock_ti814x.c | 224 static void pll_config(u32 base, u32 n, u32 m, u32 m2, in pll_config() function
309 pll_config(MPU_PLL_BASE, MPU_N, MPU_M, MPU_M2, MPU_CLKCTRL, 0); in mpu_pll_config()
324 pll_config(L3_PLL_BASE, L3_N, L3_M, L3_M2, L3_CLKCTRL, 1); in l3_pll_config()
329 pll_config(DDR_PLL_BASE, DDR_N, DDR_M, DDR_M2, DDR_CLKCTRL, 1); in ddr_pll_config()
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| /rk3399_rockchip-uboot/drivers/clk/renesas/ |
| H A D | clk-rcar-gen3.c | 794 const struct rcar_gen3_cpg_pll_config *pll_config = in gen3_clk_get_rate() local
837 rate = gen3_clk_get_rate(&parent) / pll_config->extal_div; in gen3_clk_get_rate()
840 core->parent, pll_config->extal_div, rate); in gen3_clk_get_rate()
852 rate = gen3_clk_get_rate(&parent) * pll_config->pll1_mult; in gen3_clk_get_rate()
855 core->parent, pll_config->pll1_mult, rate); in gen3_clk_get_rate()
867 rate = gen3_clk_get_rate(&parent) * pll_config->pll3_mult; in gen3_clk_get_rate()
870 core->parent, pll_config->pll3_mult, rate); in gen3_clk_get_rate()
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| /rk3399_rockchip-uboot/arch/arm/mach-socfpga/ |
| H A D | qts-filter.sh | 120 ${in_bsp_dir}/generated/pll_config.h |
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| /rk3399_rockchip-uboot/drivers/clk/rockchip/ |
| H A D | clk_rk3368.c | 872 struct pll_div pll_config = {0}; in rk3368_armclk_set_clk() local
889 ret = pll_para_config(hz, &pll_config, &pll_div); in rk3368_armclk_set_clk()
904 ret = rkclk_set_pll(priv->cru, pll_id, &pll_config); in rk3368_armclk_set_clk()
922 ret = rkclk_set_pll(priv->cru, pll_id, &pll_config); in rk3368_armclk_set_clk()
1000 struct pll_div pll_config = {0}; in rk3368_clk_set_rate() local
1010 ret = pll_para_config(rate, &pll_config, &pll_div); in rk3368_clk_set_rate()
1014 ret = rkclk_set_pll(priv->cru, clk->id - 1, &pll_config); in rk3368_clk_set_rate()
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| /rk3399_rockchip-uboot/doc/ |
| H A D | README.socfpga | 131 pll_config.h
143 -rw-r--r-- 1 sarnold sarnold 3190 Mar 21 18:11 pll_config.h
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