Home
last modified time | relevance | path

Searched refs:pe (Results 1 – 9 of 9) sorted by relevance

/rk3399_rockchip-uboot/drivers/net/
H A Dmvpp2.c1419 static int mvpp2_prs_hw_write(struct mvpp2 *priv, struct mvpp2_prs_entry *pe) in mvpp2_prs_hw_write() argument
1423 if (pe->index > MVPP2_PRS_TCAM_SRAM_SIZE - 1) in mvpp2_prs_hw_write()
1427 pe->tcam.word[MVPP2_PRS_TCAM_INV_WORD] &= ~MVPP2_PRS_TCAM_INV_MASK; in mvpp2_prs_hw_write()
1430 mvpp2_write(priv, MVPP2_PRS_TCAM_IDX_REG, pe->index); in mvpp2_prs_hw_write()
1432 mvpp2_write(priv, MVPP2_PRS_TCAM_DATA_REG(i), pe->tcam.word[i]); in mvpp2_prs_hw_write()
1435 mvpp2_write(priv, MVPP2_PRS_SRAM_IDX_REG, pe->index); in mvpp2_prs_hw_write()
1437 mvpp2_write(priv, MVPP2_PRS_SRAM_DATA_REG(i), pe->sram.word[i]); in mvpp2_prs_hw_write()
1443 static int mvpp2_prs_hw_read(struct mvpp2 *priv, struct mvpp2_prs_entry *pe) in mvpp2_prs_hw_read() argument
1447 if (pe->index > MVPP2_PRS_TCAM_SRAM_SIZE - 1) in mvpp2_prs_hw_read()
1451 mvpp2_write(priv, MVPP2_PRS_TCAM_IDX_REG, pe->index); in mvpp2_prs_hw_read()
[all …]
/rk3399_rockchip-uboot/drivers/video/tegra124/
H A Ddisplayport.h293 static inline int tegra_dp_is_max_vs(u32 pe, u32 vs) in tegra_dp_is_max_vs() argument
295 return (vs < (DRIVECURRENT_LEVEL3 - pe)) ? 0 : 1; in tegra_dp_is_max_vs()
298 static inline int tegra_dp_is_max_pe(u32 pe, u32 vs) in tegra_dp_is_max_pe() argument
300 return (pe < (PREEMPHASIS_LEVEL3 - vs)) ? 0 : 1; in tegra_dp_is_max_pe()
H A Ddp.c865 static int tegra_dp_lt_adjust(struct tegra_dp_priv *dp, u32 pe[4], u32 vs[4], in tegra_dp_lt_adjust()
879 pe[2 * cnt] = (data_ptr & NV_DPCD_ADJUST_REQ_LANEX_PE_MASK) >> in tegra_dp_lt_adjust()
883 pe[1 + 2 * cnt] = in tegra_dp_lt_adjust()
1008 static int tegra_dp_lt_config(struct tegra_dp_priv *dp, u32 pe[4], u32 vs[4], in tegra_dp_lt_config()
1044 pe_reg = tegra_dp_pe_regs[pc[cnt]][vs[cnt]][pe[cnt]]; in tegra_dp_lt_config()
1045 vs_reg = tegra_dp_vs_regs[pc[cnt]][vs[cnt]][pe[cnt]]; in tegra_dp_lt_config()
1046 pc_reg = tegra_dp_pc_regs[pc[cnt]][vs[cnt]][pe[cnt]]; in tegra_dp_lt_config()
1057 u32 max_vs_flag = tegra_dp_is_max_vs(pe[cnt], vs[cnt]); in tegra_dp_lt_config()
1058 u32 max_pe_flag = tegra_dp_is_max_pe(pe[cnt], vs[cnt]); in tegra_dp_lt_config()
1064 (pe[cnt] << NV_DPCD_TRAINING_LANEX_SET_PE_SHIFT) | in tegra_dp_lt_config()
[all …]
/rk3399_rockchip-uboot/lib/rsa/
H A Drsa-sign.c324 static int rsa_engine_init(const char *engine_id, ENGINE **pe) in rsa_engine_init() argument
350 *pe = e; in rsa_engine_init()
/rk3399_rockchip-uboot/drivers/video/drm/
H A Danalogix_dp_reg.c791 u8 vs, pe; in analogix_dp_set_lane_link_training() local
799 pe = (training_lane & DP_TRAIN_PRE_EMPHASIS_MASK) >> in analogix_dp_set_lane_link_training()
802 phy_cfg.dp.pre[lane] = pe; in analogix_dp_set_lane_link_training()
H A Ddw-dp.c597 unsigned int lanes = link->lanes, *vs, *pe; in dw_dp_link_train_update_vs_emph() local
602 pe = request->pre_emphasis; in dw_dp_link_train_update_vs_emph()
606 phy_cfg.dp.pre[i] = pe[i]; in dw_dp_link_train_update_vs_emph()
619 (pe[i] << DP_TRAIN_PRE_EMPHASIS_SHIFT); in dw_dp_link_train_update_vs_emph()
/rk3399_rockchip-uboot/arch/arm/dts/
H A Dsun9i-a80-cubieboard4.dts225 regulator-name = "vcc-pe";
H A Dsun9i-a80-optimus.dts297 regulator-name = "vcc-pe";
/rk3399_rockchip-uboot/drivers/ata/
H A Dsata_dwc.c169 struct ata_probe_ent *pe; member