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Searched refs:p0 (Results 1 – 18 of 18) sorted by relevance

/rk3399_rockchip-uboot/arch/nds32/cpu/n1213/
H A Dstart.S318 mfsr $p0, $MMU_CFG
319 andi $p0, $p0, 0x3 ! MMPS
321 bne $p0, $p1, 1f
328 mfsr $p0, MR_CAC_CTL ! Get the $CACHE_CTL reg
330 and $p0, $p0, $p1 ! Set DC_EN bit
331 mtsr $p0, MR_CAC_CTL ! write back the $CACHE_CTL reg
346 andi $p0, $t0, ICAC_MEM_KBF_ISZ
348 ! if $p0=0, then no I CAC existed
349 beqz $p0, end_flush_icache
351 ! get $p0 the index of I$ block
[all …]
/rk3399_rockchip-uboot/arch/nds32/cpu/n1213/ag101/
H A Dwatchdog.S20 li $p0, (CONFIG_FTWDT010_BASE+WD_CR) ! Get the addr of WD CR
21 lwi $p1, [$p0] ! Get the config of WD
25 sw $p1, [$p0] ! Write back to WD CR
/rk3399_rockchip-uboot/arch/arm/mach-omap2/omap3/
H A Dclock.c125 int xip_safe, p0, p1, p2, p3; in dpll3_init_34xx() local
201 p0 = readl(&prcm_base->clken_pll); in dpll3_init_34xx()
202 clrsetbits_le32(&p0, 0x00000007, PLL_FAST_RELOCK_BYPASS); in dpll3_init_34xx()
204 clrsetbits_le32(&p0, 0x000000F0, ptr->fsel << 4); in dpll3_init_34xx()
228 (*f_lock_pll) (p0, p1, p2, p3); in dpll3_init_34xx()
382 int xip_safe, p0, p1, p2, p3; in dpll3_init_36xx() local
451 p0 = readl(&prcm_base->clken_pll); in dpll3_init_36xx()
452 clrsetbits_le32(&p0, 0x00000007, PLL_FAST_RELOCK_BYPASS); in dpll3_init_36xx()
454 clrsetbits_le32(&p0, 0x000000F0, ptr->fsel << 4); in dpll3_init_36xx()
478 (*f_lock_pll) (p0, p1, p2, p3); in dpll3_init_36xx()
/rk3399_rockchip-uboot/arch/arm/dts/
H A Dzynqmp-zc1751-xm015-dc1.dts148 ceva,p0-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>;
149 ceva,p0-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>;
150 ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
151 ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
H A Dzynqmp-ep108.dts145 ceva,p0-cominit-params = /bits/ 8 <0x0F 0x25 0x18 0x29>;
146 ceva,p0-comwake-params = /bits/ 8 <0x04 0x0B 0x08 0x0F>;
147 ceva,p0-burst-params = /bits/ 8 <0x0A 0x08 0x4A 0x06>;
148 ceva,p0-retry-params = /bits/ 16 <0x0216 0x7F06>;
H A Dzynqmp-zcu102-revA.dts594 ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
595 ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
596 ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
597 ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
H A Ddra71-evm.dts147 p0 {
H A Dimx6ul.dtsi526 reg_3p0: regulator-3p0 {
580 phy-3p0-supply = <&reg_3p0>;
589 phy-3p0-supply = <&reg_3p0>;
H A Dimx6ull.dtsi618 reg_3p0: regulator-3p0@120 {
672 phy-3p0-supply = <&reg_3p0>;
681 phy-3p0-supply = <&reg_3p0>;
H A Dimx6sll.dtsi510 reg_3p0: regulator-3p0@120 {
540 phy-3p0-supply = <&reg_3p0>;
H A Dimx6sl.dtsi535 regulator-3p0 {
H A Dimx6qdl.dtsi639 regulator-3p0 {
H A Dimx6sx.dtsi581 regulator-3p0 {
/rk3399_rockchip-uboot/include/optee_include/
H A Dtee_client_api.h199 #define TEEC_PARAM_TYPES(p0, p1, p2, p3) \ argument
200 ((p0) | ((p1) << 4) | ((p2) << 8) | ((p3) << 12))
/rk3399_rockchip-uboot/arch/nds32/include/asm/
H A Dptrace.h41 NDS32_REG p0; /* r26 - used by OS */ member
/rk3399_rockchip-uboot/arch/nds32/lib/
H A Dinterrupts.c82 regs->p1, regs->p0, regs->r[25], regs->r[24]); in show_regs()
/rk3399_rockchip-uboot/arch/arm/mach-rockchip/rk3308/
H A Drk3308.c187 #define QOS_PRIORITY_P1_P0(p1, p0) ((((p1) & 0x3) << 8) |\ argument
188 (((p0) & 0x3) << 0))
/rk3399_rockchip-uboot/lib/
H A Dbch.c236 const uint32_t *pdata, *p0, *p1, *p2, *p3; in encode_bch() local
275 p0 = tab0 + (l+1)*((w >> 0) & 0xff); in encode_bch()
281 r[i] = r[i+1]^p0[i]^p1[i]^p2[i]^p3[i]; in encode_bch()
283 r[l] = p0[l]^p1[l]^p2[l]^p3[l]; in encode_bch()