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Searched refs:mhz (Results 1 – 12 of 12) sorted by relevance

/rk3399_rockchip-uboot/arch/xtensa/lib/
H A Dtime.c53 ulong mhz = CONFIG_SYS_CLK_FREQ / 1000000; in __udelay() local
60 delay_cycles(mhz << 22); in __udelay()
61 delay_cycles(mhz * lo); in __udelay()
/rk3399_rockchip-uboot/arch/xtensa/cpu/
H A Dcpu.c31 char buf[120], mhz[8]; in print_cpuinfo() local
39 XCHAL_CORE_ID, id0, id1, strmhz(mhz, gd->cpu_clk)); in print_cpuinfo()
/rk3399_rockchip-uboot/drivers/ram/rockchip/
H A Dsdram_rk3328.c81 u32 mhz = hz / MHZ; in rkclk_set_dpll() local
84 if (mhz <= 300) { in rkclk_set_dpll()
87 } else if (mhz <= 400) { in rkclk_set_dpll()
90 } else if (mhz <= 600) { in rkclk_set_dpll()
93 } else if (mhz <= 800) { in rkclk_set_dpll()
96 } else if (mhz <= 1600) { in rkclk_set_dpll()
103 fbdiv = (mhz * refdiv * postdiv1 * postdiv2) / 24; in rkclk_set_dpll()
H A Dsdram_px30.c80 u32 mhz = hz / MHz; in rkclk_set_dpll() local
83 if (mhz <= 300) { in rkclk_set_dpll()
86 } else if (mhz <= 400) { in rkclk_set_dpll()
89 } else if (mhz <= 600) { in rkclk_set_dpll()
92 } else if (mhz <= 800) { in rkclk_set_dpll()
95 } else if (mhz <= 1600) { in rkclk_set_dpll()
102 fbdiv = (mhz * refdiv * postdiv1 * postdiv2) / 24; in rkclk_set_dpll()
H A Dsdram_rv1126.c325 u32 mhz = hz / MHz; in rkclk_set_dpll() local
336 if (mhz <= 100) { in rkclk_set_dpll()
339 } else if (mhz <= 150) { in rkclk_set_dpll()
342 } else if (mhz <= 200) { in rkclk_set_dpll()
345 } else if (mhz <= 300) { in rkclk_set_dpll()
348 } else if (mhz <= 400) { in rkclk_set_dpll()
355 fbdiv = (mhz * refdiv * postdiv1 * postdiv2) / 24; in rkclk_set_dpll()
1710 u32 mhz) in data_training_rd() argument
1827 u32 mhz, u32 dst_fsp) in data_training_wr() argument
1837 if (dramtype == LPDDR3 && mhz <= 400) { in data_training_wr()
[all …]
H A Dsdram_rk3399.c421 u32 mhz; member
519 if (io->mhz >= sdram_params->base.ddr_freq && in get_io_set()
523 if (io->mhz >= sdram_params->base.ddr_freq) in get_io_set()
/rk3399_rockchip-uboot/arch/arm/dts/
H A Dimx6sx-sabreauto.dts139 pinctrl_usdhc3_100mhz: usdhc3grp-100mhz {
154 pinctrl_usdhc3_200mhz: usdhc3grp-200mhz {
H A Drk3588s.dtsi96 capacity-dmips-mhz = <530>;
104 capacity-dmips-mhz = <530>;
112 capacity-dmips-mhz = <530>;
120 capacity-dmips-mhz = <530>;
128 capacity-dmips-mhz = <1024>;
136 capacity-dmips-mhz = <1024>;
144 capacity-dmips-mhz = <1024>;
152 capacity-dmips-mhz = <1024>;
H A Drk3576.dtsi427 capacity-dmips-mhz = <485>;
437 capacity-dmips-mhz = <485>;
447 capacity-dmips-mhz = <485>;
457 capacity-dmips-mhz = <485>;
467 capacity-dmips-mhz = <1024>;
477 capacity-dmips-mhz = <1024>;
487 capacity-dmips-mhz = <1024>;
497 capacity-dmips-mhz = <1024>;
/rk3399_rockchip-uboot/doc/device-tree-bindings/clock/
H A Drockchip,rk3188-cru.txt34 - "xin27m" - 27mhz crystal input on rk3066 - optional,
/rk3399_rockchip-uboot/arch/arm/mach-tegra/tegra124/
H A Dclock.c1071 mhz = 1000 * 1000, min_vco = 500 * mhz, max_vco = 1000 * mhz, in clock_set_display_rate() local
1072 min_cf = 1 * mhz, max_cf = 6 * mhz; in clock_set_display_rate()
/rk3399_rockchip-uboot/board/hisilicon/hikey/
H A DREADME123 INFO: lpddr3_freq_init, set ddrc 533mhz
126 INFO: lpddr3_freq_init, set ddrc 800mhz