Lines Matching refs:mhz
325 u32 mhz = hz / MHz; in rkclk_set_dpll() local
336 if (mhz <= 100) { in rkclk_set_dpll()
339 } else if (mhz <= 150) { in rkclk_set_dpll()
342 } else if (mhz <= 200) { in rkclk_set_dpll()
345 } else if (mhz <= 300) { in rkclk_set_dpll()
348 } else if (mhz <= 400) { in rkclk_set_dpll()
355 fbdiv = (mhz * refdiv * postdiv1 * postdiv2) / 24; in rkclk_set_dpll()
1710 u32 mhz) in data_training_rd() argument
1827 u32 mhz, u32 dst_fsp) in data_training_wr() argument
1837 if (dramtype == LPDDR3 && mhz <= 400) { in data_training_wr()
1927 if (dramtype == LPDDR3 && mhz <= 400) { in data_training_wr()