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/rk3399_rockchip-uboot/doc/device-tree-bindings/net/
H A Dti,dp83867.txt5 - ti,rx-internal-delay - RGMII Recieve Clock Delay - see dt-bindings/net/ti-dp83867.h
7 - ti,tx-internal-delay - RGMII Transmit Clock Delay - see dt-bindings/net/ti-dp83867.h
19 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
20 ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_75_NS>;
/rk3399_rockchip-uboot/arch/arm/dts/
H A Ddra72-evm-revc.dts67 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
68 ti,tx-internal-delay = <DP83867_RGMIIDCTL_250_PS>;
75 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
76 ti,tx-internal-delay = <DP83867_RGMIIDCTL_250_PS>;
H A Dzynqmp-zcu102-revB.dts21 ti,rx-internal-delay = <0x8>;
22 ti,tx-internal-delay = <0xa>;
H A Ddra71-evm.dts185 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
186 ti,tx-internal-delay = <DP83867_RGMIIDCTL_250_PS>;
193 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
194 ti,tx-internal-delay = <DP83867_RGMIIDCTL_250_PS>;
H A Darmada-xp-gp.dts50 * internal registers to 0xf1000000 (instead of the default
54 * left internal registers mapped at 0xd0000000. If you are in this
83 * the address range used for I/O (internal registers,
152 internal-regs {
H A Darmada-xp-maxbcm.dts49 * internal registers to 0xf1000000 (instead of the default
53 * left internal registers mapped at 0xd0000000. If you are in this
82 * the address range used for I/O (internal registers,
151 internal-regs {
/rk3399_rockchip-uboot/doc/device-tree-bindings/remoteproc/
H A Dremoteproc.txt11 - remoteproc-internal-memory-mapped: a bool, indicates that the remote
12 processor has internal memory that it uses to execute code and store
/rk3399_rockchip-uboot/arch/mips/dts/
H A Dnexys4ddr.dts32 xlnx,include-internal-loopback = <0x0>;
38 xlnx,use-internal = <0x0>;
/rk3399_rockchip-uboot/board/microchip/pic32mzda/
H A DREADME11 This processor boots with proprietary stage1 bootloader running from internal
13 on internal program-flash. Finally U-Boot loads OS image (along with other
/rk3399_rockchip-uboot/board/congatec/conga-qeval20-qa3-e3845/
H A DREADME16 conga-qeval20-qa3-e3845-internal-uart_defconfig
18 provides the U-Boot console on the BayTrail internal legacy UART,
H A DMAINTAINERS8 F: configs/conga-qeval20-qa3-e3845-internal-uart_defconfig
/rk3399_rockchip-uboot/fs/yaffs2/
H A Dyaffs_allocator.c128 curr->internal[0] = next; in yaffs_create_tnodes()
132 curr->internal[0] = allocator->free_tnodes; in yaffs_create_tnodes()
175 allocator->free_tnodes = allocator->free_tnodes->internal[0]; in yaffs_alloc_raw_tnode()
193 tn->internal[0] = allocator->free_tnodes; in yaffs_free_raw_tnode()
/rk3399_rockchip-uboot/doc/
H A DREADME.m68k42 internal FLASH.
86 make EB+MCF-EV123_internal_config for internal FLASH
112 -- defines the base address of the MCF5272 internal SRAM
135 CONFIG_SYS_MBAR -- defines the base address of the MCF5282 internal register space
137 -- defines the base address of the MCF5282 internal SRAM
139 -- defines the base address of the MCF5282 internal Flash memory
H A DREADME.nokia_rx516 internal eMMC memory via twl4030 regulator which is not enabled by NOLO.
15 SD card or internal eMMC memory. If this fails or keyboard is closed then
32 * 2. try boot from internal eMMC memory
52 * run emmcboot - Boot from internal eMMC memory (see boot order)
69 * mmc ${mmcnum} (0 - external, 1 - internal)
H A DREADME.fdt-overlays8 Please refer to dt-object-internal.txt in the dtc sources for information
9 regarding the internal format of overlays:
10 https://git.kernel.org/pub/scm/utils/dtc/dtc.git/tree/Documentation/dt-object-internal.txt
/rk3399_rockchip-uboot/board/keymile/km_arm/
H A Dkwbimage_128M16_1.cfg199 # bit 15-12: 4, internal ODT time based on bit 7-4
200 # with the considered SDRAM internal delay
201 # bit 19-16: 8, internal ODT de-assertion based on bit 11-8
202 # with the considered SDRAM internal delay
208 # bit 11-8: 4, internal ODT assertion 2 cycles after write start command
209 # with the considered SDRAM internal delay
210 # bit 15-12: 8, internal ODT de-assertion 5 cycles after write start command
211 # with the considered SDRAM internal delay
H A Dkwbimage_256M8_1.cfg201 # bit 15-12: 4, internal ODT time based on bit 7-4
202 # with the considered SDRAM internal delay
203 # bit 19-16: 8, internal ODT de-assertion based on bit 11-8
204 # with the considered SDRAM internal delay
210 # bit 11-8: 4, internal ODT assertion 2 cycles after write start command
211 # with the considered SDRAM internal delay
212 # bit 15-12: 8, internal ODT de-assertion 5 cycles after write start command
213 # with the considered SDRAM internal delay
H A Dkwbimage-memphis.cfg137 # bit15-12: 0100, internal ODT assertion 4 cycles after read
138 # bit19-16: 1000, internal ODT de-assertion 8 cycles after read
144 # bit11-8 : 0100, internal ODT assertion x cycles after write
145 # bit15-12: 1000, internal ODT de-assertion x cycles after write
/rk3399_rockchip-uboot/board/buffalo/lsxl/
H A Dkwbimage-lschl.cfg143 # bit15-12: 5, 5 cycles from read command to assertion of internal ODT signal
144 # bit19-16: 8, 8 cycles from read command to de-assertion of internal ODT signal
151 # bit15-12: 5, 5 cycles from write command to assertion of internal ODT signal
152 # bit19-16: 8, 8 cycles from write command to de-assertion of internal ODT signal
196 # bit3-0: 0b1111, internal ODT is asserted during read from DRAM bank 0-3
197 # bit7-4: 0b0000, internal ODT is not asserted during write to DRAM bank 0-3
H A Dkwbimage-lsxhl.cfg143 # bit15-12: 5, 5 cycles from read command to assertion of internal ODT signal
144 # bit19-16: 8, 8 cycles from read command to de-assertion of internal ODT signal
151 # bit15-12: 5, 5 cycles from write command to assertion of internal ODT signal
152 # bit19-16: 8, 8 cycles from write command to de-assertion of internal ODT signal
196 # bit3-0: 0b1111, internal ODT is asserted during read from DRAM bank 0-3
197 # bit7-4: 0b0000, internal ODT is not asserted during write to DRAM bank 0-3
/rk3399_rockchip-uboot/arch/x86/include/asm/arch-baytrail/acpi/
H A Dglobal_nvs.asl14 IURE, 8, /* internal UART enabled */
/rk3399_rockchip-uboot/board/d-link/dns325/
H A Dkwbimage.cfg132 # bit15-12: 5, 5 cycles from read command to assertion of internal ODT signal
133 # bit19-16: 8, 8 cycles from read command to de-assertion of internal ODT signal
139 # bit15-12: 5, 5 cycles from write command to assertion of internal ODT signal
140 # bit19-16: 8, 8 cycles from write command to de-assertion of internal ODT signal
176 # bit3-0: 0b0011, internal ODT is asserted during read from DRAM bank 0-1
177 # bit7-4: 0b0000, internal ODT is not asserted during write to DRAM bank 0-4
/rk3399_rockchip-uboot/
H A DKbuild41 # We use internal kbuild rules to avoid the "is up to date" message from make
62 # We use internal kbuild rules to avoid the "is up to date" message from make
/rk3399_rockchip-uboot/drivers/usb/eth/
H A DKconfig30 This driver supports the internal PHY.
39 This driver supports the internal PHY.
/rk3399_rockchip-uboot/arch/xtensa/dts/
H A Dxtfpga.dtsi30 /* one cell: internal irq number,
31 * two cells: second cell == 0: internal irq number

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