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/rk3399_rockchip-uboot/doc/
H A DREADME.mxsimage23 Each configuration file uses very simple instruction semantics and a few
27 - Each line of the configuration file contains exactly one instruction.
31 - Each "section" is started by the "SECTION" instruction.
32 - The "SECTION" instruction has the following semantics:
43 - A "SECTION" must be immediatelly followed by a "TAG" instruction.
44 - The "TAG" instruction has the following semantics:
53 - This instruction does nothing
62 - i.MX28-specific instruction!
67 - i.MX28-specific instruction!
82 - See JUMP instruction above, as the operation is exactly the same with
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H A DREADME.NDS327 AndeStar is a patent-pending 16-bit/32-bit mixed-length instruction set to
11 - Intermixable 32-bit and 16-bit instruction sets without the need for
14 - RISC-style register-based instruction set.
29 - Three instruction extension space for application acceleration:
H A DREADME.POST437 the expected one. The mcrxr instruction will be tested by
443 (mtcrf), executing each instruction several times to modify all
456 description of each test case: the instruction, the values of
498 that very point. For the bl instruction the value of the link
500 instruction various combinations of the BI/BO fields, the CTR
516 entry will contain: the instruction opcode, the value of the
518 executing the instruction, the test will verify the contents of
521 table entry will contain: the instruction opcode, the array
523 of the destination register. After executing the instruction,
592 To verify the instruction cache operation the following test
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H A DREADME.bedbug31 if it is an illegal instruction, privileged instruction or
H A DREADME.s5pc1xx15 While ARM Cortex-A8 support ARM v7 instruction set (-march=armv7a) we compile
H A DREADME.N12137 - 16-/32-bit mixable instruction format.
H A DREADME.rmobile18 ARM Cortex-A9 support ARM v7 instruction set (-march=armv7a).
H A DREADME.xtensa71 instruction to determine the stack frame size, and adjusting the stack
H A DREADME.omap329 While ARM Cortex-A8 support ARM v7 instruction set (-march=armv7a) we compile
H A DREADME.memory-test79 cache use (instruction fetching, cache flushing). So far I am not
H A DREADME.m54418twr213 icache - enable or disable instruction cache
H A DREADME.chromium151 The instruction are similar to those for Nyan with changes as noted below:
/rk3399_rockchip-uboot/doc/device-tree-bindings/cpu/
H A Dnios2.txt16 - icache-line-size: Contains instruction line size.
18 - icache-size: Contains instruction cache size.
23 - altr,has-initda: Specifies CPU support initda instruction, should be 1.
/rk3399_rockchip-uboot/board/work-microwave/work_92105/
H A Dwork_92105_display.c133 static void hd44780_instruction(unsigned long instruction) in hd44780_instruction() argument
138 max6957aax_write(MAX6957AAX_HD44780_DATA, instruction); in hd44780_instruction()
141 if (instruction == HD44780_CLEAR_DISPLAY) in hd44780_instruction()
/rk3399_rockchip-uboot/drivers/mtd/
H A Dst_smi.c293 unsigned int instruction; in smi_sector_erase() local
313 instruction = ((sect_add >> 8) & 0x0000FF00) | SECTOR_ERASE; in smi_sector_erase()
329 writel(instruction, &smicntl->smi_tr); in smi_sector_erase()
/rk3399_rockchip-uboot/board/freescale/bsc9131rdb/
H A DREADME46 . 32-Kbyte L1 instruction cache
54 . 32 Kbyte 8-way level 1 instruction cache (L1 ICache)
56 . 512 Kbyte 8-way level 2 unified instruction/data cache (M2 memory)
/rk3399_rockchip-uboot/arch/x86/cpu/ivybridge/
H A DKconfig50 without resorting to software trapping and/or instruction set
/rk3399_rockchip-uboot/board/congatec/cgtqmx6eval/
H A DREADME70 these instruction will produce the same effect:
/rk3399_rockchip-uboot/board/freescale/bsc9132qds/
H A DREADME46 - 32 KB, 8-way, level 1 instruction cache (L1 ICache)
48 - 512 KB, 8-way, level 2 unified instruction/data cache (L2 cache/M2 memory)
/rk3399_rockchip-uboot/arch/arm/
H A DKconfig242 bool "Build U-Boot using the Thumb instruction set"
245 Use this flag to build U-Boot using the Thumb instruction set for
246 ARM architectures. Thumb instruction set provides better code
251 bool "Build SPL using the Thumb instruction set"
255 Use this flag to build SPL using the Thumb instruction set for
256 ARM architectures. Thumb instruction set provides better code
261 bool "Build TPL using the Thumb instruction set"
265 Use this flag to build SPL using the Thumb instruction set for
266 ARM architectures. Thumb instruction set provides better code
/rk3399_rockchip-uboot/board/ti/ks2_evm/
H A DREADME149 to "SPI Little Endian Boot mode" as per instruction at
169 to "ARM NAND Boot mode" as per instruction at
189 1. Set the SW3 dip switch to "ARM MMC Boot mode" as per instruction at
/rk3399_rockchip-uboot/arch/arm/lib/
H A Dvectors.S244 movs pc, lr @ jump to next instruction & switch modes.
/rk3399_rockchip-uboot/arch/arm/cpu/armv7/
H A Dnonsec_virt.S82 orreq r5, r5, #0x100 @ allow HVC instruction
/rk3399_rockchip-uboot/arch/arm/cpu/armv8/
H A DKconfig13 cluster, and for A57/A72, it enables receiving of instruction
/rk3399_rockchip-uboot/board/freescale/m52277evb/
H A DREADME206 icache - enable or disable instruction cache

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