env: Convert CONFIG_ENV_IS_IN... to a choice

At present we support multiple environment drivers but there is not way to
select between them at run time. Also settings related to the position and
siz

env: Convert CONFIG_ENV_IS_IN... to a choice

At present we support multiple environment drivers but there is not way to
select between them at run time. Also settings related to the position and
size of the environment area are global (i.e. apply to all locations).

Until these limitations are removed we cannot really support more than one
environment location. Adjust the location to be a choice so that only one
can be selected. By default the environment is 'nowhere', meaning that the
environment exists only in memory and cannot be saved.

Also expand the help for the 'nowhere' option and move it to the top since
it is the default.

Signed-off-by: Simon Glass <sjg@chromium.org>
[trini: Move all of the imply logic to default X if Y so it works again]
Signed-off-by: Tom Rini <trini@konsulko.com>

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Merge git://git.denx.de/u-boot-x86

x86: Switch all boards to use DM SCSI

After MMC is converted to DM, convert to use DM SCSI as well for all
x86 boards and imply BLK for both MMC and SCSI drivers.

CONFIG_SCSI_DEV_LIST is no longer

x86: Switch all boards to use DM SCSI

After MMC is converted to DM, convert to use DM SCSI as well for all
x86 boards and imply BLK for both MMC and SCSI drivers.

CONFIG_SCSI_DEV_LIST is no longer used. Clean them up.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

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x86: Convert INTEL_ICH6_GPIO to Kconfig

This converts Intel ICH6 GPIO driver to Kconfig, and add it to the
imply list of platform drivers.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by:

x86: Convert INTEL_ICH6_GPIO to Kconfig

This converts Intel ICH6 GPIO driver to Kconfig, and add it to the
imply list of platform drivers.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

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x86: kconfig: Move USB to platform Kconfig

Like other peripheral drivers, move USB related drivers to platform
Kconfig as well.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Andy Shevch

x86: kconfig: Move USB to platform Kconfig

Like other peripheral drivers, move USB related drivers to platform
Kconfig as well.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

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x86: ivybridge: kconfig: Imply platform specific drivers

Imply drivers that are working with Ivybridge platform in the
platform Kconfig.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Si

x86: ivybridge: kconfig: Imply platform specific drivers

Imply drivers that are working with Ivybridge platform in the
platform Kconfig.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

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x86: kconfig: Imply ENABLE_MRC_CACHE in the platform Kconfig

Platform knows whether MRC cache is implemented, but using it can
be a choice of a specific board.

Signed-off-by: Bin Meng <bmeng.cn@gma

x86: kconfig: Imply ENABLE_MRC_CACHE in the platform Kconfig

Platform knows whether MRC cache is implemented, but using it can
be a choice of a specific board.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

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x86: kconfig: Imply HAVE_INTEL_ME in the platform Kconfig

Intel Management Engine is required by the platform, however it's
not a must have when building a U-Boot image. For example, during
developm

x86: kconfig: Imply HAVE_INTEL_ME in the platform Kconfig

Intel Management Engine is required by the platform, however it's
not a must have when building a U-Boot image. For example, during
development normally programming ME firmware is a one-time effort.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

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x86: Move common MRC Kconfig options to the common file

At present the MRC options are private to ivybridge. Other Intel CPUs also
use these settings. Move them to a common place.

Signed-off-by: Si

x86: Move common MRC Kconfig options to the common file

At present the MRC options are private to ivybridge. Other Intel CPUs also
use these settings. Move them to a common place.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

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x86: Add Intel Cougar Canyon 2 board

This adds basic support to Intel Cougar Canyon 2 board, a board
based on Chief River platform with an Ivy Bridge processor and
a Panther Point chipset.

Signed-o

x86: Add Intel Cougar Canyon 2 board

This adds basic support to Intel Cougar Canyon 2 board, a board
based on Chief River platform with an Ivy Bridge processor and
a Panther Point chipset.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>

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x86: ivybridge: Add FSP support

IvyBridge FSP package is built with a base address at 0xfff80000,
and does not use UPD data region. This adds basic FSP support.

Signed-off-by: Bin Meng <bmeng.cn@gm

x86: ivybridge: Add FSP support

IvyBridge FSP package is built with a base address at 0xfff80000,
and does not use UPD data region. This adds basic FSP support.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested on link (ivybridge non-FSP)
Tested-by: Simon Glass <sjg@chromium.org>

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Merge branch 'master' of git://git.denx.de/u-boot-x86

x86: ivybridge: Do not require HAVE_INTEL_ME

Do not set HAVE_INTEL_ME by default as for some cases Intel ME
firmware even does not reside on the same SPI flash as U-Boot.

Signed-off-by: Bin Meng <b

x86: ivybridge: Do not require HAVE_INTEL_ME

Do not set HAVE_INTEL_ME by default as for some cases Intel ME
firmware even does not reside on the same SPI flash as U-Boot.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>

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x86: Remove CPU_INTEL_SOCKET_RPGA989

This Kconfig option name indicates it has something to do with cpu
socket, however it is actually not the case. Remove it and move
options inside it to NORTHBRID

x86: Remove CPU_INTEL_SOCKET_RPGA989

This Kconfig option name indicates it has something to do with cpu
socket, however it is actually not the case. Remove it and move
options inside it to NORTHBRIDGE_INTEL_IVYBRIDGE.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>

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x86: Clean up ivybridge/chrome Kconfig options

There are some options which are never used, and also some options
which are selected by others but have never been a Kconfg option.
Clean these up.

S

x86: Clean up ivybridge/chrome Kconfig options

There are some options which are never used, and also some options
which are selected by others but have never been a Kconfg option.
Clean these up.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>

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x86: ivybridge: Remove NORTHBRIDGE_INTEL_SANDYBRIDGE

NORTHBRIDGE_INTEL_SANDYBRIDGE is for sandybridge, not ivybridge.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromiu

x86: ivybridge: Remove NORTHBRIDGE_INTEL_SANDYBRIDGE

NORTHBRIDGE_INTEL_SANDYBRIDGE is for sandybridge, not ivybridge.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>

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Merge branch 'master' of git://git.denx.de/u-boot

Merge git://git.denx.de/u-boot-x86

x86: ivybridge: Remove SMP from CPU_SPECIFIC_OPTIONS

Ivybridge is not ready for U-Boot MP initialization yet.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>

Merge branch 'master' of git://git.denx.de/u-boot

Merge branch 'master' of git://git.denx.de/u-boot-x86

x86: ivybridge: Drop the Kconfig MRC cache information

This is now stored in the device tree.

Signed-off-by: Simon Glass <sjg@chromium.org>

Merge git://git.denx.de/u-boot-x86

Conflicts:
arch/x86/cpu/Makefile

Signed-off-by: Tom Rini <trini@ti.com>

x86: ivybridge: Implement SDRAM init

Implement SDRAM init using the Memory Reference Code (mrc.bin) provided in
the board directory and the SDRAM SPD information in the device tree. This
also needs

x86: ivybridge: Implement SDRAM init

Implement SDRAM init using the Memory Reference Code (mrc.bin) provided in
the board directory and the SDRAM SPD information in the device tree. This
also needs the Intel Management Engine (me.bin) to work. Binary blobs
everywhere: so far we have MRC, ME and microcode.

SDRAM init works by setting up various parameters and calling the MRC. This
in turn does some sort of magic to work out how much memory there is and
the timing parameters to use. It also sets up the DRAM controllers. When
the MRC returns, we use the information it provides to map out the
available memory in U-Boot.

U-Boot normally moves itself to the top of RAM. On x86 the RAM is not
generally contiguous, and anyway some RAM may be above 4GB which doesn't
work in 32-bit mode. So we relocate to the top of the largest block of
RAM we can find below 4GB. Memory above 4GB is accessible with special
functions (see physmem).

It would be possible to build U-Boot in 64-bit mode but this wouldn't
necessarily provide any more memory, since the largest block is often below
4GB. Anyway U-Boot doesn't need huge amounts of memory - even a very large
ramdisk seldom exceeds 100-200MB. U-Boot has support for booting 64-bit
kernels directly so this does not pose a limitation in that area. Also there
are probably parts of U-Boot that will not work correctly in 64-bit mode.
The MRC is one.

There is some work remaining in this area. Since memory init is very slow
(over 500ms) it is possible to save the parameters in SPI flash to speed it
up next time. Suspend/resume support is not fully implemented, or at least
it is not efficient.

With this patch, link boots to a prompt.

Signed-off-by: Simon Glass <sjg@chromium.org>

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x86: Add chromebook_link board

This board is a 'bare' version of the existing 'link 'board. It does not
require coreboot to run, but is intended to start directly from the reset
vector.

This initia

x86: Add chromebook_link board

This board is a 'bare' version of the existing 'link 'board. It does not
require coreboot to run, but is intended to start directly from the reset
vector.

This initial commit has place holders for a wide range of features. These
will be added in follow-on patches and series. So far it cannot be booted
as there is no ROM image produced, but it does build without errors.

Signed-off-by: Simon Glass <sjg@chromium.org>

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