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Searched refs:impedance (Results 1 – 13 of 13) sorted by relevance

/rk3399_rockchip-uboot/arch/arm/dts/
H A Dzynq-zc706.dts161 bias-high-impedance;
241 bias-high-impedance;
254 bias-high-impedance;
275 bias-high-impedance;
298 bias-high-impedance;
H A Dzynq-zc702.dts215 bias-high-impedance;
238 bias-high-impedance;
322 bias-high-impedance;
335 bias-high-impedance;
356 bias-high-impedance;
379 bias-high-impedance;
H A Ddra72-evm-revc.dts70 ti,min-output-impedance;
78 ti,min-output-impedance;
H A Ddra71-evm.dts188 ti,impedance-control = <0x1f>;
196 ti,impedance-control = <0x1f>;
H A Dtegra124-cei-tk1-som.dts109 bias-high-impedance;
H A Dtegra124-jetson-tk1.dts108 bias-high-impedance;
H A Drk3288-tinker.dtsi375 nuvoton,vref-impedance = <2>;
H A Dtegra124-nyan.dtsi140 bias-high-impedance;
H A Dtegra124-apalis.dts1689 bias-high-impedance;
/rk3399_rockchip-uboot/arch/arm/mach-exynos/
H A Dclock_init.h135 unsigned impedance; /* drive strength impedeance */ member
H A Ddmc_init_ddr3.c52 val = (mem->impedance << CA_CK_DRVR_DS_OFFSET) | in ddr3_mem_ctrl_init()
53 (mem->impedance << CA_CKE_DRVR_DS_OFFSET) | in ddr3_mem_ctrl_init()
54 (mem->impedance << CA_CS_DRVR_DS_OFFSET) | in ddr3_mem_ctrl_init()
55 (mem->impedance << CA_ADR_DRVR_DS_OFFSET); in ddr3_mem_ctrl_init()
H A Dclock_init_exynos5.c368 .impedance = IMP_OUTPUT_DRV_30_OHM,
471 .impedance = IMP_OUTPUT_DRV_40_OHM,
/rk3399_rockchip-uboot/doc/device-tree-bindings/pinctrl/
H A Dpinctrl-bindings.txt205 bias-high-impedance - high impedance mode ("third-state", "floating")