1*77b55e8cSThomas Abraham /* 2*77b55e8cSThomas Abraham * Clock initialization routines 3*77b55e8cSThomas Abraham * 4*77b55e8cSThomas Abraham * Copyright (c) 2011 The Chromium OS Authors. 5*77b55e8cSThomas Abraham * 6*77b55e8cSThomas Abraham * SPDX-License-Identifier: GPL-2.0+ 7*77b55e8cSThomas Abraham */ 8*77b55e8cSThomas Abraham 9*77b55e8cSThomas Abraham #ifndef __EXYNOS_CLOCK_INIT_H 10*77b55e8cSThomas Abraham #define __EXYNOS_CLOCK_INIT_H 11*77b55e8cSThomas Abraham 12*77b55e8cSThomas Abraham enum { 13*77b55e8cSThomas Abraham #ifdef CONFIG_EXYNOS5420 14*77b55e8cSThomas Abraham MEM_TIMINGS_MSR_COUNT = 5, 15*77b55e8cSThomas Abraham #else 16*77b55e8cSThomas Abraham MEM_TIMINGS_MSR_COUNT = 4, 17*77b55e8cSThomas Abraham #endif 18*77b55e8cSThomas Abraham }; 19*77b55e8cSThomas Abraham 20*77b55e8cSThomas Abraham /* These are the ratio's for configuring ARM clock */ 21*77b55e8cSThomas Abraham struct arm_clk_ratios { 22*77b55e8cSThomas Abraham unsigned arm_freq_mhz; /* Frequency of ARM core in MHz */ 23*77b55e8cSThomas Abraham 24*77b55e8cSThomas Abraham unsigned apll_mdiv; 25*77b55e8cSThomas Abraham unsigned apll_pdiv; 26*77b55e8cSThomas Abraham unsigned apll_sdiv; 27*77b55e8cSThomas Abraham 28*77b55e8cSThomas Abraham unsigned arm2_ratio; 29*77b55e8cSThomas Abraham unsigned apll_ratio; 30*77b55e8cSThomas Abraham unsigned pclk_dbg_ratio; 31*77b55e8cSThomas Abraham unsigned atb_ratio; 32*77b55e8cSThomas Abraham unsigned periph_ratio; 33*77b55e8cSThomas Abraham unsigned acp_ratio; 34*77b55e8cSThomas Abraham unsigned cpud_ratio; 35*77b55e8cSThomas Abraham unsigned arm_ratio; 36*77b55e8cSThomas Abraham }; 37*77b55e8cSThomas Abraham 38*77b55e8cSThomas Abraham /* These are the memory timings for a particular memory type and speed */ 39*77b55e8cSThomas Abraham struct mem_timings { 40*77b55e8cSThomas Abraham enum mem_manuf mem_manuf; /* Memory manufacturer */ 41*77b55e8cSThomas Abraham enum ddr_mode mem_type; /* Memory type */ 42*77b55e8cSThomas Abraham unsigned frequency_mhz; /* Frequency of memory in MHz */ 43*77b55e8cSThomas Abraham 44*77b55e8cSThomas Abraham /* Here follow the timing parameters for the selected memory */ 45*77b55e8cSThomas Abraham unsigned apll_mdiv; 46*77b55e8cSThomas Abraham unsigned apll_pdiv; 47*77b55e8cSThomas Abraham unsigned apll_sdiv; 48*77b55e8cSThomas Abraham unsigned mpll_mdiv; 49*77b55e8cSThomas Abraham unsigned mpll_pdiv; 50*77b55e8cSThomas Abraham unsigned mpll_sdiv; 51*77b55e8cSThomas Abraham unsigned cpll_mdiv; 52*77b55e8cSThomas Abraham unsigned cpll_pdiv; 53*77b55e8cSThomas Abraham unsigned cpll_sdiv; 54*77b55e8cSThomas Abraham unsigned gpll_mdiv; 55*77b55e8cSThomas Abraham unsigned gpll_pdiv; 56*77b55e8cSThomas Abraham unsigned gpll_sdiv; 57*77b55e8cSThomas Abraham unsigned epll_mdiv; 58*77b55e8cSThomas Abraham unsigned epll_pdiv; 59*77b55e8cSThomas Abraham unsigned epll_sdiv; 60*77b55e8cSThomas Abraham unsigned vpll_mdiv; 61*77b55e8cSThomas Abraham unsigned vpll_pdiv; 62*77b55e8cSThomas Abraham unsigned vpll_sdiv; 63*77b55e8cSThomas Abraham unsigned bpll_mdiv; 64*77b55e8cSThomas Abraham unsigned bpll_pdiv; 65*77b55e8cSThomas Abraham unsigned bpll_sdiv; 66*77b55e8cSThomas Abraham unsigned kpll_mdiv; 67*77b55e8cSThomas Abraham unsigned kpll_pdiv; 68*77b55e8cSThomas Abraham unsigned kpll_sdiv; 69*77b55e8cSThomas Abraham unsigned dpll_mdiv; 70*77b55e8cSThomas Abraham unsigned dpll_pdiv; 71*77b55e8cSThomas Abraham unsigned dpll_sdiv; 72*77b55e8cSThomas Abraham unsigned ipll_mdiv; 73*77b55e8cSThomas Abraham unsigned ipll_pdiv; 74*77b55e8cSThomas Abraham unsigned ipll_sdiv; 75*77b55e8cSThomas Abraham unsigned spll_mdiv; 76*77b55e8cSThomas Abraham unsigned spll_pdiv; 77*77b55e8cSThomas Abraham unsigned spll_sdiv; 78*77b55e8cSThomas Abraham unsigned rpll_mdiv; 79*77b55e8cSThomas Abraham unsigned rpll_pdiv; 80*77b55e8cSThomas Abraham unsigned rpll_sdiv; 81*77b55e8cSThomas Abraham unsigned pclk_cdrex_ratio; 82*77b55e8cSThomas Abraham unsigned direct_cmd_msr[MEM_TIMINGS_MSR_COUNT]; 83*77b55e8cSThomas Abraham 84*77b55e8cSThomas Abraham unsigned timing_ref; 85*77b55e8cSThomas Abraham unsigned timing_row; 86*77b55e8cSThomas Abraham unsigned timing_data; 87*77b55e8cSThomas Abraham unsigned timing_power; 88*77b55e8cSThomas Abraham 89*77b55e8cSThomas Abraham /* DQS, DQ, DEBUG offsets */ 90*77b55e8cSThomas Abraham unsigned phy0_dqs; 91*77b55e8cSThomas Abraham unsigned phy1_dqs; 92*77b55e8cSThomas Abraham unsigned phy0_dq; 93*77b55e8cSThomas Abraham unsigned phy1_dq; 94*77b55e8cSThomas Abraham unsigned phy0_tFS; 95*77b55e8cSThomas Abraham unsigned phy1_tFS; 96*77b55e8cSThomas Abraham unsigned phy0_pulld_dqs; 97*77b55e8cSThomas Abraham unsigned phy1_pulld_dqs; 98*77b55e8cSThomas Abraham 99*77b55e8cSThomas Abraham unsigned lpddr3_ctrl_phy_reset; 100*77b55e8cSThomas Abraham unsigned ctrl_start_point; 101*77b55e8cSThomas Abraham unsigned ctrl_inc; 102*77b55e8cSThomas Abraham unsigned ctrl_start; 103*77b55e8cSThomas Abraham unsigned ctrl_dll_on; 104*77b55e8cSThomas Abraham unsigned ctrl_ref; 105*77b55e8cSThomas Abraham 106*77b55e8cSThomas Abraham unsigned ctrl_force; 107*77b55e8cSThomas Abraham unsigned ctrl_rdlat; 108*77b55e8cSThomas Abraham unsigned ctrl_bstlen; 109*77b55e8cSThomas Abraham 110*77b55e8cSThomas Abraham unsigned fp_resync; 111*77b55e8cSThomas Abraham unsigned iv_size; 112*77b55e8cSThomas Abraham unsigned dfi_init_start; 113*77b55e8cSThomas Abraham unsigned aref_en; 114*77b55e8cSThomas Abraham 115*77b55e8cSThomas Abraham unsigned rd_fetch; 116*77b55e8cSThomas Abraham 117*77b55e8cSThomas Abraham unsigned zq_mode_dds; 118*77b55e8cSThomas Abraham unsigned zq_mode_term; 119*77b55e8cSThomas Abraham unsigned zq_mode_noterm; /* 1 to allow termination disable */ 120*77b55e8cSThomas Abraham 121*77b55e8cSThomas Abraham unsigned memcontrol; 122*77b55e8cSThomas Abraham unsigned memconfig; 123*77b55e8cSThomas Abraham 124*77b55e8cSThomas Abraham unsigned membaseconfig0; 125*77b55e8cSThomas Abraham unsigned membaseconfig1; 126*77b55e8cSThomas Abraham unsigned prechconfig_tp_cnt; 127*77b55e8cSThomas Abraham unsigned dpwrdn_cyc; 128*77b55e8cSThomas Abraham unsigned dsref_cyc; 129*77b55e8cSThomas Abraham unsigned concontrol; 130*77b55e8cSThomas Abraham /* Channel and Chip Selection */ 131*77b55e8cSThomas Abraham uint8_t dmc_channels; /* number of memory channels */ 132*77b55e8cSThomas Abraham uint8_t chips_per_channel; /* number of chips per channel */ 133*77b55e8cSThomas Abraham uint8_t chips_to_configure; /* number of chips to configure */ 134*77b55e8cSThomas Abraham uint8_t send_zq_init; /* 1 to send this command */ 135*77b55e8cSThomas Abraham unsigned impedance; /* drive strength impedeance */ 136*77b55e8cSThomas Abraham uint8_t gate_leveling_enable; /* check gate leveling is enabled */ 137*77b55e8cSThomas Abraham uint8_t read_leveling_enable; /* check h/w read leveling is enabled */ 138*77b55e8cSThomas Abraham }; 139*77b55e8cSThomas Abraham 140*77b55e8cSThomas Abraham /** 141*77b55e8cSThomas Abraham * Get the correct memory timings for our selected memory type and speed. 142*77b55e8cSThomas Abraham * 143*77b55e8cSThomas Abraham * This function can be called from SPL or the main U-Boot. 144*77b55e8cSThomas Abraham * 145*77b55e8cSThomas Abraham * @return pointer to the memory timings that we should use 146*77b55e8cSThomas Abraham */ 147*77b55e8cSThomas Abraham struct mem_timings *clock_get_mem_timings(void); 148*77b55e8cSThomas Abraham 149*77b55e8cSThomas Abraham /* 150*77b55e8cSThomas Abraham * Initialize clock for the device 151*77b55e8cSThomas Abraham */ 152*77b55e8cSThomas Abraham void system_clock_init(void); 153*77b55e8cSThomas Abraham 154*77b55e8cSThomas Abraham /* 155*77b55e8cSThomas Abraham * Set clock divisor value for booting from EMMC. 156*77b55e8cSThomas Abraham */ 157*77b55e8cSThomas Abraham void emmc_boot_clk_div_set(void); 158*77b55e8cSThomas Abraham #endif 159