Searched refs:freq_val (Results 1 – 7 of 7) sorted by relevance
158 extern u32 freq_val[];204 extern u32 freq_val[];217 extern u32 freq_val[DDR_FREQ_LIMIT];259 extern u32 freq_val[DDR_FREQ_LIMIT];283 extern u32 freq_val[];296 extern u32 freq_val[];
158 u32 adll_period = MEGA / freq_val[frequency] / 64; in ddr3_tip_write_leveling_static_config()218 u32 sdr_period = MEGA / freq_val[frequency]; in ddr3_tip_read_leveling_static_config()219 u32 ddr_period = MEGA / freq_val[frequency] / 2; in ddr3_tip_read_leveling_static_config()220 u32 adll_period = MEGA / freq_val[frequency] / 64; in ddr3_tip_read_leveling_static_config()
368 t_ckclk = (MEGA / freq_val[freq]); in hws_ddr3_tip_init_controller()661 adll_tap = MEGA / (freq_val[freq] * 64); in hws_ddr3_tip_init_controller()677 freq_val[DDR_FREQ_LOW_FREQ] = dfs_low_freq; in hws_ddr3_tip_load_topology_map()700 speed_bin_index, freq_val[freq], in hws_ddr3_tip_load_topology_map()1196 mdelay(100 / (freq_val[frequency] / freq_val[DDR_FREQ_LOW_FREQ])); in adll_calibration()1379 t_hclk = MEGA / (freq_val[frequency] / 2); in ddr3_tip_freq_set()1453 mdelay(100 / (freq_val[frequency] / freq_val[DDR_FREQ_LOW_FREQ])); in ddr3_tip_freq_set()1480 adll_tap = MEGA / (freq_val[frequency] * 64); in ddr3_tip_freq_set()1631 t_ckclk = (MEGA / freq_val[frequency]); in ddr3_tip_set_timing()2040 freq_val[low_freq])); in ddr3_tip_ddr3_training_main_flow()[all …]
605 divider = a38x_vco_freq_per_sar[sar_val] / freq_val[frequency]; in ddr3_tip_a38x_set_divider()661 if ((frequency == DDR_FREQ_LOW_FREQ) || (freq_val[frequency] <= 400)) { in ddr3_tip_a38x_set_divider()
16 u32 freq_val[DDR_FREQ_LIMIT] = { variable
43 int adll_tap = MEGA / freq_val[medium_freq] / 64; in ddr3_tip_pbs()
917 *ptr = (u32 *)&(freq_val[DDR_FREQ_LOW_FREQ]); in ddr3_tip_access_atr()