Lines Matching refs:freq_val
368 t_ckclk = (MEGA / freq_val[freq]); in hws_ddr3_tip_init_controller()
661 adll_tap = MEGA / (freq_val[freq] * 64); in hws_ddr3_tip_init_controller()
677 freq_val[DDR_FREQ_LOW_FREQ] = dfs_low_freq; in hws_ddr3_tip_load_topology_map()
700 speed_bin_index, freq_val[freq], in hws_ddr3_tip_load_topology_map()
1196 mdelay(100 / (freq_val[frequency] / freq_val[DDR_FREQ_LOW_FREQ])); in adll_calibration()
1379 t_hclk = MEGA / (freq_val[frequency] / 2); in ddr3_tip_freq_set()
1453 mdelay(100 / (freq_val[frequency] / freq_val[DDR_FREQ_LOW_FREQ])); in ddr3_tip_freq_set()
1480 adll_tap = MEGA / (freq_val[frequency] * 64); in ddr3_tip_freq_set()
1631 t_ckclk = (MEGA / freq_val[frequency]); in ddr3_tip_set_timing()
2040 freq_val[low_freq])); in ddr3_tip_ddr3_training_main_flow()
2078 freq_val[medium_freq])); in ddr3_tip_ddr3_training_main_flow()
2096 if ((rl_mid_freq_wa == 0) || (freq_val[medium_freq] == 533)) { in ddr3_tip_ddr3_training_main_flow()
2138 if ((rl_mid_freq_wa == 0) || (freq_val[medium_freq] == 533)) { in ddr3_tip_ddr3_training_main_flow()
2214 freq_val[tm-> in ddr3_tip_ddr3_training_main_flow()