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Searched refs:ecc_ena (Results 1 – 8 of 8) sorted by relevance

/rk3399_rockchip-uboot/drivers/ddr/marvell/axp/
H A Dddr3_hw_training.c108 dram_info.ecc_ena = 1; in ddr3_hw_training()
112 dram_info.ecc_ena = 0; in ddr3_hw_training()
121 dram_info.num_of_total_pups = ddr_width / PUP_SIZE + dram_info.ecc_ena; in ddr3_hw_training()
452 if (dram_info.ecc_ena) { in ddr3_hw_training()
722 dram_info->ecc_ena) in ddr3_save_training()
953 if (dram_info->ecc_ena) { in ddr3_training_suspend_resume()
H A Dddr3_write_leveling.c113 && dram_info->ecc_ena) in ddr3_write_leveling_hw()
142 && dram_info->ecc_ena) in ddr3_write_leveling_hw()
238 for (ecc = 0; ecc < (dram_info->ecc_ena + 1); in ddr3_wl_supplement()
256 (dram_info->ecc_ena * in ddr3_wl_supplement()
412 if (dram_info->ecc_ena) in ddr3_wl_supplement()
435 && dram_info->ecc_ena) in ddr3_wl_supplement()
536 && dram_info->ecc_ena) in ddr3_write_leveling_hw_reg_dimm()
H A Dddr3_read_leveling.c104 && dram_info->ecc_ena) in ddr3_read_leveling_hw()
135 && dram_info->ecc_ena) in ddr3_read_leveling_hw()
206 for (ecc = 0; ecc <= (dram_info->ecc_ena); ecc++) { in ddr3_read_leveling_sw()
210 reg |= (dram_info->ecc_ena * in ddr3_read_leveling_sw()
267 pup < (dram_info->num_of_std_pups + dram_info->ecc_ena); in ddr3_read_leveling_sw()
285 pup < (dram_info->num_of_std_pups + dram_info->ecc_ena); in ddr3_read_leveling_sw()
H A Dddr3_pbs.c136 for (ecc = 0; ecc < (dram_info->ecc_ena + 1); ecc++) { in ddr3_pbs_tx()
162 reg |= (dram_info->ecc_ena * ecc << in ddr3_pbs_tx()
372 if (pup == (max_pup - 1) && dram_info->ecc_ena) in ddr3_pbs_tx()
579 for (ecc = 0; ecc < (dram_info->ecc_ena + 1); ecc++) { in ddr3_pbs_rx()
604 reg |= (dram_info->ecc_ena * ecc << in ddr3_pbs_rx()
1430 if (pup == (max_pup - 1) && dram_info->ecc_ena) in ddr3_set_pbs_results()
H A Dddr3_init.h118 int ddr3_dunit_setup(u32 ecc_ena, u32 hclk_time, u32 *ddr_width);
H A Dddr3_dqs.c156 for (ecc = 0; ecc < (dram_info->ecc_ena + 1); ecc++) { in ddr3_dqs_centralization_rx()
161 reg |= (dram_info->ecc_ena * in ddr3_dqs_centralization_rx()
237 for (ecc = 0; ecc < (dram_info->ecc_ena + 1); ecc++) { in ddr3_dqs_centralization_tx()
241 reg |= (dram_info->ecc_ena * in ddr3_dqs_centralization_tx()
H A Dddr3_hw_training.h259 u32 ecc_ena; /* 0/1 */ member
H A Dddr3_spd.c575 int ddr3_dunit_setup(u32 ecc_ena, u32 hclk_time, u32 *ddr_width) argument
716 if (ecc_ena && ddr3_get_min_val(sum_info.err_check_type, dimm_num,