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Searched refs:dpcd (Results 1 – 5 of 5) sorted by relevance

/rk3399_rockchip-uboot/drivers/video/drm/
H A Ddrm_dp_helper.c109 void drm_dp_link_train_clock_recovery_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) in drm_dp_link_train_clock_recovery_delay()
111 int rd_interval = dpcd[DP_TRAINING_AUX_RD_INTERVAL] & in drm_dp_link_train_clock_recovery_delay()
117 if (rd_interval == 0 || dpcd[DP_DPCD_REV] >= DP_DPCD_REV_14) in drm_dp_link_train_clock_recovery_delay()
123 void drm_dp_link_train_channel_eq_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) in drm_dp_link_train_channel_eq_delay()
125 int rd_interval = dpcd[DP_TRAINING_AUX_RD_INTERVAL] & in drm_dp_link_train_channel_eq_delay()
240 u8 dpcd[DP_RECEIVER_CAP_SIZE]) in drm_dp_read_extended_dpcd_caps()
252 if (!(dpcd[DP_TRAINING_AUX_RD_INTERVAL] & in drm_dp_read_extended_dpcd_caps()
263 if (dpcd[DP_DPCD_REV] > dpcd_ext[DP_DPCD_REV]) { in drm_dp_read_extended_dpcd_caps()
265 aux->name, dpcd[DP_DPCD_REV], dpcd_ext[DP_DPCD_REV]); in drm_dp_read_extended_dpcd_caps()
269 if (!memcmp(dpcd, dpcd_ext, sizeof(dpcd_ext))) in drm_dp_read_extended_dpcd_caps()
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H A Danalogix_dp.c109 enhanced_frame_en = drm_dp_enhanced_frame_cap(dp->dpcd); in analogix_dp_set_enhanced_mode()
178 assr_en = drm_dp_alternate_scrambler_reset_cap(dp->dpcd); in analogix_dp_set_assr_mode()
362 u8 dpcd = 0; in analogix_dp_tps3_supported() local
366 drm_dp_dpcd_readb(&dp->aux, DP_MAX_LANE_COUNT, &dpcd); in analogix_dp_tps3_supported()
367 sink_tps3_supported = dpcd & DP_TPS3_SUPPORTED; in analogix_dp_tps3_supported()
379 drm_dp_link_train_clock_recovery_delay(dp->dpcd); in analogix_dp_process_clock_recovery()
460 drm_dp_link_train_channel_eq_delay(dp->dpcd); in analogix_dp_process_equalizer_training()
695 u8 dpcd; in analogix_dp_init_training() local
712 drm_dp_dpcd_readb(&dp->aux, DP_MAX_DOWNSPREAD, &dpcd); in analogix_dp_init_training()
713 dp->link_train.ssc = !!(dpcd & DP_MAX_DOWNSPREAD_0_5); in analogix_dp_init_training()
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H A Ddw-dp.c195 u8 dpcd[DP_RECEIVER_CAP_SIZE]; member
560 u8 dpcd; in dw_dp_link_probe() local
564 ret = drm_dp_read_dpcd_caps(&dp->aux, link->dpcd); in dw_dp_link_probe()
569 &dpcd); in dw_dp_link_probe()
574 !!(dpcd & DP_VSC_SDP_EXT_FOR_COLORIMETRY_SUPPORTED); in dw_dp_link_probe()
576 link->revision = link->dpcd[DP_DPCD_REV]; in dw_dp_link_probe()
578 drm_dp_max_link_rate(link->dpcd)); in dw_dp_link_probe()
580 drm_dp_max_lane_count(link->dpcd)); in dw_dp_link_probe()
582 link->caps.enhanced_framing = drm_dp_enhanced_frame_cap(link->dpcd); in dw_dp_link_probe()
583 link->caps.tps3_supported = drm_dp_tps3_supported(link->dpcd); in dw_dp_link_probe()
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H A Danalogix_dp.h665 u8 dpcd[DP_RECEIVER_CAP_SIZE]; member
/rk3399_rockchip-uboot/include/drm/
H A Ddrm_dp_helper.h1019 void drm_dp_link_train_clock_recovery_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]);
1020 void drm_dp_link_train_channel_eq_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]);
1117 drm_dp_max_link_rate(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) in drm_dp_max_link_rate()
1119 return drm_dp_bw_code_to_link_rate(dpcd[DP_MAX_LINK_RATE]); in drm_dp_max_link_rate()
1123 drm_dp_max_lane_count(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) in drm_dp_max_lane_count()
1125 return dpcd[DP_MAX_LANE_COUNT] & DP_MAX_LANE_COUNT_MASK; in drm_dp_max_lane_count()
1129 drm_dp_enhanced_frame_cap(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) in drm_dp_enhanced_frame_cap()
1131 return dpcd[DP_DPCD_REV] >= 0x11 && in drm_dp_enhanced_frame_cap()
1132 (dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP); in drm_dp_enhanced_frame_cap()
1136 drm_dp_tps3_supported(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) in drm_dp_tps3_supported()
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