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Searched refs:divm (Results 1 – 6 of 6) sorted by relevance

/rk3399_rockchip-uboot/arch/arm/mach-tegra/
H A Dclock.c90 int clock_ll_read_pll(enum clock_id clkid, u32 *divm, u32 *divn, in clock_ll_read_pll() argument
103 *divm = (data >> pllinfo->m_shift) & pllinfo->m_mask; in clock_ll_read_pll()
114 unsigned long clock_start_pll(enum clock_id clkid, u32 divm, u32 divn, in clock_start_pll() argument
148 data = (divm << pllinfo->m_shift) | (divn << pllinfo->n_shift); in clock_start_pll()
536 u32 base, divm; in clock_get_rate() local
553 divm = (base >> pllinfo->m_shift) & pllinfo->m_mask; in clock_get_rate()
567 divm <<= (base >> pllinfo->p_shift) & pllinfo->p_mask; in clock_get_rate()
568 do_div(rate, divm); in clock_get_rate()
H A Dcpu.c171 int pllx_set_rate(struct clk_pll_simple *pll , u32 divn, u32 divm, in pllx_set_rate() argument
188 reg = PLL_BYPASS_MASK | (divm << pllinfo->m_shift); in pllx_set_rate()
/rk3399_rockchip-uboot/arch/arm/include/asm/arch-tegra/
H A Dclock.h62 unsigned long clock_start_pll(enum clock_id id, u32 divm, u32 divn,
89 int clock_ll_read_pll(enum clock_id clkid, u32 *divm, u32 *divn,
H A Dwarmboot.h72 u32 divm:5; member
/rk3399_rockchip-uboot/arch/arm/mach-tegra/tegra20/
H A Dwarmboot.c154 u32 divm, divn, divp, cpcon, lfcon; in warmboot_save_sdram_params() local
156 if (clock_ll_read_pll(CLOCK_ID_MEMORY, &divm, &divn, &divp, in warmboot_save_sdram_params()
159 scratch2.pllm_base_divm = divm; in warmboot_save_sdram_params()
/rk3399_rockchip-uboot/arch/arm/mach-tegra/tegra124/
H A Dclock.c1067 u32 divm, divn, divp, cpcon; in clock_set_display_rate() local
1087 for (divm = 1; divm < max_m && best_diff; divm++) { in clock_set_display_rate()
1088 cf = ref / divm; in clock_set_display_rate()
1108 best_m = divm; in clock_set_display_rate()