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Searched refs:div2 (Results 1 – 7 of 7) sorted by relevance

/rk3399_rockchip-uboot/arch/arm/mach-sunxi/
H A Dclock_sun8i_a83t.c112 unsigned int div1 = 0, div2 = 0; in clock_set_pll5() local
117 div2 << CCM_PLL5_DIV2_SHIFT | in clock_set_pll5()
133 int div2 = ((rval & CCM_PLL6_CTRL_DIV2_MASK) >> in clock_get_pll6() local
135 return 24000000 * n / div1 / div2; in clock_get_pll6()
/rk3399_rockchip-uboot/arch/arm/mach-s5pc1xx/include/mach/
H A Dclock.h31 unsigned int div2; member
67 unsigned int div2; member
/rk3399_rockchip-uboot/drivers/video/drm/rk628/
H A Drk628_cru.c135 u64 foutvco, foutpostdiv, div1, div2; in rk628_cru_clk_set_rate_pll() local
178 div2 = DIV_ROUND_UP(MAX_FVCO_RATE, fout); in rk628_cru_clk_set_rate_pll()
179 for (postdiv = div1; postdiv <= div2; postdiv++) { in rk628_cru_clk_set_rate_pll()
193 if (postdiv > div2) in rk628_cru_clk_set_rate_pll()
/rk3399_rockchip-uboot/arch/arm/mach-keystone/include/mach/
H A Dclock_defs.h23 u32 div2; /* 1c */ member
/rk3399_rockchip-uboot/arch/arm/dts/
H A Dls1021a.dtsi125 clock-output-names = "cga-pll1", "cga-pll1-div2",
134 clock-output-names = "platform-clk", "platform-clk-div2";
141 clock-names = "pll1cga", "pll1cga-div2", "pll1cga-div4";
H A Dstih407-clock.dtsi76 clock-output-names = "clk-m-a9-ext2f-div2";
H A Dstih410-clock.dtsi78 clock-output-names = "clk-m-a9-ext2f-div2";