| /rk3399_rockchip-uboot/board/freescale/common/ |
| H A D | ics307_clk.c | 143 in_8(&fpga_reg->dclk[0]), in get_board_ddr_clk()
144 in_8(&fpga_reg->dclk[1]), in get_board_ddr_clk()
145 in_8(&fpga_reg->dclk[2])); in get_board_ddr_clk()
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| H A D | ngpixis.c | 145 PIXIS_READ(dclk[0]), PIXIS_READ(dclk[1]), PIXIS_READ(dclk[2])); in pixis_dump_regs()
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| H A D | qixis.c | 185 printf("dclk = %02x%02x%02x\n", QIXIS_READ(dclk[0]), in qixis_dump_regs()
186 QIXIS_READ(dclk[1]), QIXIS_READ(dclk[2])); in qixis_dump_regs()
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| H A D | pixis.h | 35 u8 dclk[3]; member
98 u8 dclk[3]; member
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| H A D | ngpixis.h | 40 u8 dclk[3]; member
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| H A D | qixis.h | 49 u8 dclk[3]; member
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| /rk3399_rockchip-uboot/drivers/misc/ |
| H A D | rockchip_decompress.c | 91 struct clk dclk; member
264 ret = clk_get_by_index(dev, 1, &priv->dclk); in rockchip_decom_probe()
268 ret = clk_set_rate(&priv->dclk, DCLK_DECOM); in rockchip_decom_probe()
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| /rk3399_rockchip-uboot/drivers/video/rk_eink/ |
| H A D | rk_ebc_tcon.c | 30 struct clk dclk; member
453 ret = clk_set_rate(&tcon->dclk, panel->sdck * ((panel->panel_16bit ? 7 : 3) + 1)); in ebc_tcon_enable()
721 ret = clk_set_rate(&tcon->dclk, in rk3576_ebc_tcon_enable()
801 ret = clk_get_by_name(dev, "dclk", &priv->dclk); in rk_ebc_tcon_probe()
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| /rk3399_rockchip-uboot/drivers/video/drm/ |
| H A D | rockchip_vop.c | 381 ret = clk_get_by_name(crtc_state->dev, "dclk_vop", &crtc_state->dclk); in rockchip_vop_init()
383 ret = clk_set_rate(&crtc_state->dclk, mode->crtc_clock * 1000); in rockchip_vop_init()
1018 ret = clk_set_rate(&crtc_state->dclk, 150000000); in rockchip_vop_send_mcu_cmd()
1056 ret = clk_set_rate(&crtc_state->dclk, mode->crtc_clock * 1000); in rockchip_vop_send_mcu_cmd()
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| H A D | rockchip_display.h | 201 struct clk dclk; member
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| H A D | rockchip_vop2.c | 4810 vop2_clk_set_rate(&cstate->dclk, 150000000); in rockchip_vop2_send_mcu_cmd()
4844 vop2_clk_set_rate(&cstate->dclk, mode->crtc_clock * 1000); in rockchip_vop2_send_mcu_cmd()
5147 ret = clk_get_by_name(cstate->dev, dclk_name, &cstate->dclk); in rockchip_vop2_init()
5189 vop2_clk_set_parent(&cstate->dclk, &hdmi0_phy_pll); in rockchip_vop2_init()
5191 vop2_clk_set_parent(&cstate->dclk, &hdmi1_phy_pll); in rockchip_vop2_init()
5209 ret = vop2_clk_set_rate(&cstate->dclk, in rockchip_vop2_init()
5227 ret = vop2_clk_set_rate(&cstate->dclk, dclk_rate / vp_dclk_div * 1000); in rockchip_vop2_init()
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| /rk3399_rockchip-uboot/arch/arm/dts/ |
| H A D | rk3288.dtsi | 722 reset-names = "axi", "ahb", "dclk";
766 reset-names = "axi", "ahb", "dclk";
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| H A D | rk3308.dtsi | 1194 /* dclk */
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| H A D | rk3399.dtsi | 1528 reset-names = "axi", "ahb", "dclk";
1558 reset-names = "axi", "ahb", "dclk";
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| H A D | rv1103b.dtsi | 851 clock-names = "aclk", "dclk", "pclk";
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| H A D | rv1106.dtsi | 850 clock-names = "aclk", "dclk", "pclk";
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| H A D | rk1808.dtsi | 1514 lcdc_rgb_dclk_pin: lcdc-rgb-dclk-pin {
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| H A D | rv1126.dtsi | 1318 clock-names = "aclk", "dclk", "pclk";
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| H A D | rk3576.dtsi | 1735 clock-names = "hclk", "aclk", "dclk";
3634 clock-names = "aclk", "dclk", "pclk";
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| H A D | rk3528.dtsi | 1173 "dclk",
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| H A D | rk3588s.dtsi | 1670 clock-names = "aclk", "dclk", "pclk";
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| H A D | rk3568.dtsi | 880 clock-names = "hclk", "dclk";
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| H A D | rv1126b.dtsi | 3024 clock-names = "aclk", "dclk", "pclk";
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