| /rk3399_rockchip-uboot/drivers/rkflash/ |
| H A D | nandc.c | 41 ctl_reg.d32 = 0; in nandc_init()
48 nandc_writel(ctl_reg.d32, NANDC_V9_FMCTL); in nandc_init()
53 nandc_writel(ctl_reg.d32, NANDC_FMCTL); in nandc_init()
73 tmp.d32 = nandc_readl(NANDC_FMCTL); in nandc_flash_cs()
75 nandc_writel(tmp.d32, NANDC_FMCTL); in nandc_flash_cs()
82 tmp.d32 = nandc_readl(NANDC_FMCTL); in nandc_flash_de_cs()
85 nandc_writel(tmp.d32, NANDC_FMCTL); in nandc_flash_de_cs()
103 tmp.d32 = nandc_readl(NANDC_FMCTL); in nandc_wait_flash_ready()
143 fl_reg.d32 = 0; in nandc_bch_sel()
147 nandc_writel(fl_reg.d32, NANDC_V9_FLCTL); in nandc_bch_sel()
[all …]
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| H A D | sfc_nor.c | 214 op.sfcmd.d32 = 0; in snor_write_en()
217 op.sfctrl.d32 = 0; in snor_write_en()
228 op.sfcmd.d32 = 0; in snor_reset_device()
231 op.sfctrl.d32 = 0; in snor_reset_device()
234 op.sfcmd.d32 = 0; in snor_reset_device()
237 op.sfctrl.d32 = 0; in snor_reset_device()
250 op.sfcmd.d32 = 0; in snor_enter_4byte_mode()
253 op.sfctrl.d32 = 0; in snor_enter_4byte_mode()
265 op.sfcmd.d32 = 0; in snor_read_status()
268 op.sfctrl.d32 = 0; in snor_read_status()
[all …]
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| H A D | sfc.c | 94 cmd.d32 = op->sfcmd.d32; in sfc_request()
99 ctrl.d32 = op->sfctrl.d32; in sfc_request()
109 op->sfctrl.d32 |= 0x2; in sfc_request()
117 writel(op->sfctrl.d32, g_sfc_reg + SFC_CTRL); in sfc_request()
118 writel(cmd.d32, g_sfc_reg + SFC_CMD); in sfc_request()
164 fifostat.d32 = readl(g_sfc_reg + SFC_FSR); in sfc_request()
195 fifostat.d32 = readl(g_sfc_reg + SFC_FSR); in sfc_request()
226 fifostat.d32 = readl(g_sfc_reg + SFC_FSR); in sfc_request()
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| H A D | nandc.h | 36 u32 d32; member
71 u32 d32; member
96 u32 d32; member
145 u32 d32; member
174 u32 d32; member
212 u32 d32; member
239 u32 d32; member
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| H A D | sfc_nand.c | 354 op.sfcmd.d32 = 0; in sfc_nand_write_en()
357 op.sfctrl.d32 = 0; in sfc_nand_write_en()
368 op.sfcmd.d32 = 0; in sfc_nand_rw_preset()
372 op.sfctrl.d32 = 0; in sfc_nand_rw_preset()
386 op.sfcmd.d32 = 0; in sfc_nand_read_feature()
390 op.sfctrl.d32 = 0; in sfc_nand_read_feature()
410 op.sfcmd.d32 = 0; in sfc_nand_write_feature()
415 op.sfctrl.d32 = 0; in sfc_nand_write_feature()
978 op.sfcmd.d32 = 0; in sfc_nand_erase_block()
983 op.sfctrl.d32 = 0; in sfc_nand_erase_block()
[all …]
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| H A D | sfc.h | 107 u32 d32; member
144 u32 d32; member
174 u32 d32; member
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| /rk3399_rockchip-uboot/arch/arm/include/asm/arch-rockchip/ |
| H A D | sdram_msch.h | 10 u32 d32; member
23 u32 d32; member
37 u32 d32; member
47 u32 d32; member
57 u32 d32; member
71 u32 d32; member
83 u32 d32; member
98 u32 d32; member
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| H A D | sdram_rk3328.h | 172 u32 d32; member
185 u32 d32; member
195 u32 d32; member
205 u32 d32; member
215 u32 d32; member
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| H A D | sdram_rv1108_pctl_phy.h | 234 u32 d32; member
247 u32 d32; member
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| /rk3399_rockchip-uboot/drivers/ram/rockchip/ |
| H A D | sdram_px30.c | 321 writel(noc_timings->ddrtiminga0.d32, in sdram_msch_config()
323 writel(noc_timings->ddrtimingb0.d32, in sdram_msch_config()
325 writel(noc_timings->ddrtimingc0.d32, in sdram_msch_config()
327 writel(noc_timings->devtodev0.d32, in sdram_msch_config()
329 writel(noc_timings->ddrmode.d32, &msch->ddrmode); in sdram_msch_config()
330 writel(noc_timings->ddr4timing.d32, in sdram_msch_config()
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| H A D | sdram_rk3328.c | 290 writel(noc_timings->ddrtiming.d32, &msch->ddrtiming); in sdram_msch_config()
292 writel(noc_timings->ddrmode.d32, &msch->ddrmode); in sdram_msch_config()
295 writel(noc_timings->activate.d32, &msch->activate); in sdram_msch_config()
296 writel(noc_timings->devtodev.d32, &msch->devtodev); in sdram_msch_config()
297 writel(noc_timings->ddr4timing.d32, &msch->ddr4_timing); in sdram_msch_config()
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| H A D | sdram_rv1108.c | 107 params_priv->ddr_timing_t.noc_timing.d32, in ddr_msch_cfg()
111 writel(params_priv->ddr_timing_t.activate.d32, in ddr_msch_cfg()
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| H A D | sdram_rk3399.c | 1801 writel(noc_timings->ddrtiminga0.d32, in sdram_msch_config()
1802 &msch->ddrtiminga0.d32); in sdram_msch_config()
1803 writel(noc_timings->ddrtimingb0.d32, in sdram_msch_config()
1804 &msch->ddrtimingb0.d32); in sdram_msch_config()
1805 writel(noc_timings->ddrtimingc0.d32, in sdram_msch_config()
1806 &msch->ddrtimingc0.d32); in sdram_msch_config()
1807 writel(noc_timings->devtodev0.d32, in sdram_msch_config()
1808 &msch->devtodev0.d32); in sdram_msch_config()
1809 writel(noc_timings->ddrmode.d32, in sdram_msch_config()
1810 &msch->ddrmode.d32); in sdram_msch_config()
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| H A D | sdram_rv1126.c | 2249 writel(sdram_params->ch.noc_timings.ddrtiminga0.d32, in update_noc_timing()
2251 writel(sdram_params->ch.noc_timings.ddrtimingb0.d32, in update_noc_timing()
2253 writel(sdram_params->ch.noc_timings.ddrtimingc0.d32, in update_noc_timing()
2255 writel(sdram_params->ch.noc_timings.devtodev0.d32, in update_noc_timing()
2257 writel(sdram_params->ch.noc_timings.ddrmode.d32, &dram->msch->ddrmode); in update_noc_timing()
2258 writel(sdram_params->ch.noc_timings.ddr4timing.d32, in update_noc_timing()
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| H A D | sdram_rk3308.c | 466 writel(BWRATIO_HALF_BW | params_priv->ddr_timing_t.noc_timing.d32, in ddr_msch_cfg()
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