| /rk3399_rockchip-uboot/include/faraday/ |
| H A D | ftpmu010.h | 143 #define FTPMU010_PDLLCR0_HCLKOUTDIS(cr0) (((cr0) & 0xf) << 20) argument
144 #define FTPMU010_PDLLCR0_DLLFRAG(cr0) (1 << 19) argument
148 #define FTPMU010_PDLLCR0_PLL1FRANG(cr0) (((cr0) & 0x3) << 12) argument
149 #define FTPMU010_PDLLCR0_PLL1NS(cr0) (((cr0) & 0x1ff) << 3) argument
173 void ftpmu010_sdram_clk_disable(unsigned int cr0);
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| /rk3399_rockchip-uboot/arch/x86/cpu/intel_common/ |
| H A D | car.S | 103 movl %cr0, %eax
106 movl %eax, %cr0
130 movl %cr0, %eax
132 movl %eax, %cr0
162 movl %cr0, %eax
164 movl %eax, %cr0
180 movl %cr0, %eax
182 movl %eax, %cr0
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| /rk3399_rockchip-uboot/arch/x86/cpu/ |
| H A D | start16.S | 34 movl %cr0, %eax
36 movl %eax, %cr0
44 movl %cr0, %eax
46 movl %eax, %cr0
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| H A D | call32.S | 44 movl %cr0, %eax
46 movl %eax, %cr0
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| H A D | sipi_vector.S | 53 movl %cr0, %eax
57 movl %eax, %cr0
187 mov %cr0, %eax
189 mov %eax, %cr0
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| H A D | wakeup.S | 50 movl %cr0, %eax
52 movl %eax, %cr0
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| H A D | start.S | 38 movl %cr0, %eax
40 movl %eax, %cr0
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| /rk3399_rockchip-uboot/arch/x86/cpu/i386/ |
| H A D | cpu.c | 389 unsigned long cr0; in x86_enable_caches() local
391 cr0 = read_cr0(); in x86_enable_caches()
392 cr0 &= ~(X86_CR0_NW | X86_CR0_CD); in x86_enable_caches()
393 write_cr0(cr0); in x86_enable_caches()
400 unsigned long cr0; in x86_disable_caches() local
402 cr0 = read_cr0(); in x86_disable_caches()
403 cr0 |= X86_CR0_NW | X86_CR0_CD; in x86_disable_caches()
405 write_cr0(cr0); in x86_disable_caches()
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| H A D | call64.S | 72 movl %eax, %cr0
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| H A D | interrupt.c | 71 unsigned long cr0 = 0L, cr2 = 0L, cr3 = 0L, cr4 = 0L; in dump_regs() local
114 cr0 = read_cr0(); in dump_regs()
120 cr0, cr2, cr3, cr4); in dump_regs()
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| /rk3399_rockchip-uboot/drivers/spi/ |
| H A D | designware_spi.c | 358 u32 cr0 = 0; in dw_spi_xfer() local
372 cr0 = (priv->bits_per_word - 1) | (priv->type << SPI_FRF_OFFSET) | in dw_spi_xfer()
387 cr0 &= ~SPI_TMOD_MASK; in dw_spi_xfer()
388 cr0 |= (priv->tmode << SPI_TMOD_OFFSET); in dw_spi_xfer()
401 debug("%s: cr0=%08x\n", __func__, cr0); in dw_spi_xfer()
403 if (dw_read(priv, DW_SPI_CTRL0) != cr0) in dw_spi_xfer()
404 dw_write(priv, DW_SPI_CTRL0, cr0); in dw_spi_xfer()
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| H A D | lpc32xx_ssp.c | 19 u32 cr0; member
96 writel(0x7, &lslave->regs->cr0); /* 8-bit chunks, SPI, 1 clk/bit */ in spi_setup_slave()
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| H A D | rk_spi.c | 55 uint cr0; member
376 priv->cr0 = ctrlr0; in rockchip_spi_claim_bus()
386 uint ctrlr0 = priv->cr0; in rockchip_spi_config()
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| /rk3399_rockchip-uboot/arch/x86/lib/ |
| H A D | bios_asm.S | 66 movl %cr0, %eax
68 movl %eax, %cr0
114 movl %cr0, %eax
116 movl %eax, %cr0
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| /rk3399_rockchip-uboot/drivers/power/ |
| H A D | ftpmu010.c | 69 void ftpmu010_sdram_clk_disable(unsigned int cr0) in ftpmu010_sdram_clk_disable() argument
75 pdllcr0 |= FTPMU010_PDLLCR0_HCLKOUTDIS(cr0); in ftpmu010_sdram_clk_disable()
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| /rk3399_rockchip-uboot/arch/arm/mach-sunxi/ |
| H A D | rmr_switch.S | 36 mrc 15, 0, r0, cr12, cr0, 2 @ read RMR register
38 mcr 15, 0, r0, cr12, cr0, 2 @ write RMR register
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| /rk3399_rockchip-uboot/arch/m68k/include/asm/coldfire/ |
| H A D | pwm.h | 16 u8 cr0; member
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| /rk3399_rockchip-uboot/examples/standalone/ |
| H A D | rkspi.c | 21 uint cr0; member
198 priv->cr0 = ctrlr0; in rockchip_spi_claim_bus()
208 uint ctrlr0 = priv->cr0; in rockchip_spi_config()
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| /rk3399_rockchip-uboot/include/ |
| H A D | ppc_asm.tmpl | 194 * Note: code which follows this uses cr0.eq (set if from kernel),
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