Searched refs:cntr (Results 1 – 9 of 9) sorted by relevance
45 #define CTCR_ARM_TIMER_EN_OFFS(cntr) (cntr * 2) argument46 #define CTCR_ARM_TIMER_EN_MASK(cntr) (1 << CTCR_ARM_TIMER_EN_OFFS) argument47 #define CTCR_ARM_TIMER_EN(cntr) (1 << CTCR_ARM_TIMER_EN_OFFS(cntr)) argument48 #define CTCR_ARM_TIMER_DIS(cntr) (0 << CTCR_ARM_TIMER_EN_OFFS(cntr)) argument50 #define CTCR_ARM_TIMER_AUTO_OFFS(cntr) ((cntr * 2) + 1) argument51 #define CTCR_ARM_TIMER_AUTO_MASK(cntr) (1 << 1) argument52 #define CTCR_ARM_TIMER_AUTO_EN(cntr) (1 << CTCR_ARM_TIMER_AUTO_OFFS(cntr)) argument53 #define CTCR_ARM_TIMER_AUTO_DIS(cntr) (0 << CTCR_ARM_TIMER_AUTO_OFFS(cntr)) argument
32 uint64_t cntr; in rockchip_timer_get_curr_value() local37 cntr = timebase_h << 32 | timebase_l; in rockchip_timer_get_curr_value()38 return cntr; in rockchip_timer_get_curr_value()92 uint64_t cntr = rockchip_timer_get_curr_value(priv->timer); in rockchip_timer_get_count() local95 *count = ~0ull - cntr; in rockchip_timer_get_count()
336 rm_io0_pwm1_bip_cntr_a0: rm-io0-pwm1-bip-cntr-a0 {340 rm_io0_pwm1_bip_cntr_a1: rm-io0-pwm1-bip-cntr-a1 {344 rm_io0_pwm1_bip_cntr_a2: rm-io0-pwm1-bip-cntr-a2 {348 rm_io0_pwm1_bip_cntr_a3: rm-io0-pwm1-bip-cntr-a3 {352 rm_io0_pwm1_bip_cntr_a4: rm-io0-pwm1-bip-cntr-a4 {356 rm_io0_pwm1_bip_cntr_a5: rm-io0-pwm1-bip-cntr-a5 {360 rm_io0_pwm1_bip_cntr_b0: rm-io0-pwm1-bip-cntr-b0 {364 rm_io0_pwm1_bip_cntr_b1: rm-io0-pwm1-bip-cntr-b1 {368 rm_io0_pwm1_bip_cntr_b2: rm-io0-pwm1-bip-cntr-b2 {372 rm_io0_pwm1_bip_cntr_b3: rm-io0-pwm1-bip-cntr-b3 {[all …]
325 unsigned long cntr = 0; in gen_auto_negotiate() local365 cntr++; in gen_auto_negotiate()366 } while (cntr < 200); in gen_auto_negotiate()
192 u16 cntr; /* 0x04 Count */ member
216 u16 cntr; /* 0x04 Count register */ member
123 u16 cntr; /* 0x04 Count register */ member
449 setbits_le32(&gpc_regs->cntr, PCIE_PHY_PUP_REQ); in imx6_pcie_assert_core_reset()
580 u32 cntr; member