Searched refs:cmd_sts (Results 1 – 4 of 4) sorted by relevance
391 p_rx_desc->cmd_sts = in mvgbe_init_rx_desc_ring()529 u32 cmd_sts; in mvgbe_send() local544 p_txdesc->cmd_sts = MVGBE_ZERO_PADDING | MVGBE_GEN_CRC; in mvgbe_send()545 p_txdesc->cmd_sts |= MVGBE_TX_FIRST_DESC | MVGBE_TX_LAST_DESC; in mvgbe_send()546 p_txdesc->cmd_sts |= MVGBE_BUFFER_OWNED_BY_DMA; in mvgbe_send()547 p_txdesc->cmd_sts |= MVGBE_TX_EN_INTERRUPT; in mvgbe_send()564 cmd_sts = readl(&p_txdesc->cmd_sts); in mvgbe_send()565 while (cmd_sts & MVGBE_BUFFER_OWNED_BY_DMA) { in mvgbe_send()567 if ((cmd_sts & (MVGBE_ERROR_SUMMARY | MVGBE_TX_LAST_FRAME)) == in mvgbe_send()569 cmd_sts & (MVGBE_UR_ERROR | MVGBE_RL_ERROR)) { in mvgbe_send()[all …]
408 p_rx_desc->cmd_sts = BUF_OWNED_BY_DMA | RX_EN_INT; in armdfec_init_rx_desc_ring()553 u32 cmd_sts, temp; in armdfec_send() local566 p_txdesc->cmd_sts = TX_ZERO_PADDING | TX_GEN_CRC; in armdfec_send()567 p_txdesc->cmd_sts |= TX_FIRST_DESC | TX_LAST_DESC; in armdfec_send()568 p_txdesc->cmd_sts |= BUF_OWNED_BY_DMA; in armdfec_send()569 p_txdesc->cmd_sts |= TX_EN_INT; in armdfec_send()581 cmd_sts = readl(&p_txdesc->cmd_sts); in armdfec_send()582 while (cmd_sts & BUF_OWNED_BY_DMA) { in armdfec_send()584 if ((cmd_sts & (TX_ERROR | TX_LAST_DESC)) == in armdfec_send()589 cmd_sts = readl(&p_txdesc->cmd_sts); in armdfec_send()[all …]
136 u32 cmd_sts; /* Command/status field */ member144 u32 cmd_sts; /* Descriptor command status */ member
472 u32 cmd_sts; /* Descriptor command status */ member480 u32 cmd_sts; /* Descriptor command status */ member