Searched refs:cfgr (Results 1 – 7 of 7) sorted by relevance
| /rk3399_rockchip-uboot/arch/arm/mach-stm32/stm32f4/ |
| H A D | clock.c | 146 writel(0, &STM32_RCC->cfgr); /* Reset CFGR */ in configure_clocks()
162 setbits_le32(&STM32_RCC->cfgr, (( in configure_clocks()
180 clrbits_le32(&STM32_RCC->cfgr, (RCC_CFGR_SW0 | RCC_CFGR_SW1)); in configure_clocks()
181 setbits_le32(&STM32_RCC->cfgr, RCC_CFGR_SW_PLL); in configure_clocks()
183 while ((readl(&STM32_RCC->cfgr) & RCC_CFGR_SWS_MASK) != in configure_clocks()
202 if ((readl(&STM32_RCC->cfgr) & RCC_CFGR_SWS_MASK) == in clock_get()
219 (readl(&STM32_RCC->cfgr) & RCC_CFGR_AHB_PSC_MASK) in clock_get()
225 (readl(&STM32_RCC->cfgr) & RCC_CFGR_APB1_PSC_MASK) in clock_get()
231 (readl(&STM32_RCC->cfgr) & RCC_CFGR_APB2_PSC_MASK) in clock_get()
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| /rk3399_rockchip-uboot/drivers/clk/ |
| H A D | clk_stm32f7.c | 120 writel(0, ®s->cfgr); /* Reset CFGR */ in configure_clocks()
132 setbits_le32(®s->cfgr, (( in configure_clocks()
164 clrbits_le32(®s->cfgr, (RCC_CFGR_SW0 | RCC_CFGR_SW1)); in configure_clocks()
165 setbits_le32(®s->cfgr, RCC_CFGR_SW_PLL); in configure_clocks()
167 while ((readl(®s->cfgr) & RCC_CFGR_SWS_MASK) != in configure_clocks()
188 if ((readl(®s->cfgr) & RCC_CFGR_SWS_MASK) == in stm32_clk_get_rate()
208 (readl(®s->cfgr) & RCC_CFGR_AHB_PSC_MASK) in stm32_clk_get_rate()
215 (readl(®s->cfgr) & RCC_CFGR_APB1_PSC_MASK) in stm32_clk_get_rate()
222 (readl(®s->cfgr) & RCC_CFGR_APB2_PSC_MASK) in stm32_clk_get_rate()
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| /rk3399_rockchip-uboot/drivers/gpio/ |
| H A D | atmel_pio4.c | 64 writel(reg, &port_base->cfgr); in atmel_pio4_config_io_func()
141 writel(reg, &port_base->cfgr); in atmel_pio4_set_pio_output()
167 writel(reg, &port_base->cfgr); in atmel_pio4_get_pio_input()
202 clrbits_le32(&port_base->cfgr, in atmel_pio4_direction_input()
218 clrsetbits_le32(&port_base->cfgr, in atmel_pio4_direction_output()
264 return (readl(&port_base->cfgr) & in atmel_pio4_get_function()
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| /rk3399_rockchip-uboot/arch/arm/mach-at91/include/mach/ |
| H A D | at91_mc.h | 21 u32 cfgr; /* 0x04 Configuration Register */ member
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| H A D | atmel_pio4.h | 15 u32 cfgr; /* 0x04 PIO Configuration Register */ member
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| /rk3399_rockchip-uboot/arch/arm/include/asm/arch-stm32f4/ |
| H A D | stm32.h | 43 u32 cfgr; /* RCC clock configuration */ member
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| /rk3399_rockchip-uboot/drivers/pinctrl/ |
| H A D | pinctrl-at91-pio4.c | 145 writel(conf, &bank_base->cfgr); in atmel_pinctrl_set_state()
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