Searched refs:cached (Results 1 – 8 of 8) sorted by relevance
92 int cached; /* 1: access the data through dcache; 0: no dcache */ member120 if (!priv->cached) in rockchip_decom_start()246 priv->cached = dev_read_u32_default(dev, "data-cached", 0); in rockchip_decom_ofdata_to_platdata()
3 As specified by ePAPR v1.1, the spin table needs to be in cached memory. After
59 This is useful to change the behaviors linked to some cached fuse values,
80 should be cached virtual address, for Nios II with MMU it is 0xCxxx_xxxx
548 - write the negative pattern to a cached area558 - write the zero pattern to a cached area571 - write the zero pattern to a cached area584 - write the negative pattern to a cached area
418 Enable this feature to cause MRC data to be cached in NV storage455 Sets the size of the cached area for the memory reference code.458 of cached space.
1321 data-cached = <0>;
3030 Size of non-cached memory area. This area of memory will be3046 Non-cached memory is only supported on 32-bit ARM at present.