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/rk3399_rockchip-uboot/arch/arm/mach-sunxi/
H A Dclock_sun4i.c122 int axi, ahb, apb0; in clock_set_pll1() local
136 ahb = DIV_ROUND_UP(hz/axi, 204000000); /* Max 250MHz */ in clock_set_pll1()
139 printf("CPU: %uHz, AXI/AHB/APB: %d/%d/%d\n", hz, axi, ahb, apb0); in clock_set_pll1()
143 if (ahb > 4) in clock_set_pll1()
144 ahb = 3; in clock_set_pll1()
145 else if (ahb > 2) in clock_set_pll1()
146 ahb = 2; in clock_set_pll1()
147 else if (ahb > 1) in clock_set_pll1()
148 ahb = 1; in clock_set_pll1()
150 ahb = 0; in clock_set_pll1()
[all …]
/rk3399_rockchip-uboot/arch/arm/dts/
H A Dsun50i-a64-pine64-plus-u-boot.dtsi13 reset-names = "ahb";
15 clock-names = "ahb";
H A Dsun5i-gr8.dtsi199 ahb: ahb@01c20054 { label
201 compatible = "allwinner,sun5i-a13-ahb-clk";
204 clock-output-names = "ahb";
209 assigned-clocks = <&ahb>;
217 clocks = <&ahb>;
240 compatible = "allwinner,sun5i-a13-ahb-gates-clk";
242 clocks = <&ahb>;
540 clock-names = "ahb", "mod";
553 clock-names = "ahb", "mod";
567 clock-names = "ahb", "mod";
[all …]
H A Dsun8i-v3s.dtsi106 clock-names = "ahb",
111 reset-names = "ahb";
125 clock-names = "ahb",
130 reset-names = "ahb";
144 clock-names = "ahb",
149 reset-names = "ahb";
H A Dsun5i.dtsi199 ahb: ahb@01c20054 { label
201 compatible = "allwinner,sun5i-a13-ahb-clk";
204 clock-output-names = "ahb";
209 assigned-clocks = <&ahb>;
217 clocks = <&ahb>;
407 clock-names = "ahb", "mod";
421 clock-names = "ahb", "mod";
437 clock-names = "ahb",
454 clock-names = "ahb",
471 clock-names = "ahb",
[all …]
H A Dat91sam9g15ek.dts18 ahb {
H A Dat91sam9g15.dtsi16 ahb {
H A Dat91sam9x25ek.dts17 ahb {
H A Dsun9i-a80.dtsi219 compatible = "allwinner,sun9i-a80-ahb-clk";
227 compatible = "allwinner,sun9i-a80-ahb-clk";
235 compatible = "allwinner,sun9i-a80-ahb-clk";
550 clock-names = "ahb", "mmc", "output", "sample";
552 reset-names = "ahb";
564 clock-names = "ahb", "mmc", "output", "sample";
566 reset-names = "ahb";
578 clock-names = "ahb", "mmc", "output", "sample";
580 reset-names = "ahb";
592 clock-names = "ahb", "mmc", "output", "sample";
[all …]
H A Dsun4i-a10.dtsi308 ahb: ahb@01c20054 { label
310 compatible = "allwinner,sun4i-a10-ahb-clk";
313 clock-output-names = "ahb";
318 compatible = "allwinner,sun4i-a10-ahb-gates-clk";
320 clocks = <&ahb>;
357 clocks = <&ahb>;
729 clock-names = "ahb", "mod";
742 clock-names = "ahb", "mod";
756 clock-names = "ahb", "mod";
789 clock-names = "ahb",
[all …]
H A Dat91sam9g35ek.dts18 ahb {
H A Dat91sam9g35.dtsi17 ahb {
H A Dat91sam9x35ek.dts18 ahb {
H A Dsun6i-a31.dtsi479 clock-names = "ahb",
484 reset-names = "ahb";
499 clock-names = "ahb",
504 reset-names = "ahb";
519 clock-names = "ahb",
524 reset-names = "ahb";
539 clock-names = "ahb",
544 reset-names = "ahb";
961 clock-names = "ahb", "mod";
963 reset-names = "ahb";
[all …]
H A Dsun8i-h3.dtsi169 clock-names = "ahb",
174 reset-names = "ahb";
189 clock-names = "ahb",
194 reset-names = "ahb";
209 clock-names = "ahb",
214 reset-names = "ahb";
473 reset-names = "ahb", "ephy";
475 clock-names = "ahb", "ephy";
H A Dat91sam9x35.dtsi18 ahb {
H A Dat91sam9g25.dtsi18 ahb {
H A Dat91sam9x25.dtsi19 ahb {
H A Dsun5i-a13.dtsi105 compatible = "allwinner,sun5i-a13-ahb-gates-clk";
107 clocks = <&ahb>;
225 clock-names = "ahb",
268 clock-names = "ahb", "mod",
295 clock-names = "ahb", "mod",
H A Dsama5d3_tcb1.dtsi19 ahb {
H A Dsama5d3xdm.dtsi11 ahb {
H A Dimx53.dtsi92 clock-names = "ipg", "ahb";
105 clock-names = "ipg", "ahb", "ptp";
H A Dsama5d33ek.dts22 ahb {
H A Dsama5d36ek_cmp.dts20 ahb {
H A Dsama5d31ek.dts22 ahb {

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