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Searched refs:TIMER_BASE (Results 1 – 8 of 8) sorted by relevance

/rk3399_rockchip-uboot/include/
H A Drk_timer_irq.h27 #define TIMER_BASE (0x20044000 + 0x20) /* TIMER 1 */ macro
30 #define TIMER_BASE (0x110C0000 + 0x20) /* TIMER 1 */ macro
33 #define TIMER_BASE (0xFF6B0000 + 0x20) /* TIMER 1 */ macro
36 #define TIMER_BASE (0xFF1C0000 + 0x20) /* TIMER 1 */ macro
44 #define TIMER_BASE (0xFF810000 + 0x00) /* TIMER 0 */ macro
47 #define TIMER_BASE (0xFF850000 + 0x20) /* TIMER 1 */ macro
50 #define TIMER_BASE (0xFF1a0000 + 0x20) /* TIMER 1 */ macro
58 #define TIMER_BASE (0xFF210000 + 0x00) /* TIMER 0 */ macro
61 #define TIMER_BASE (0xFF700000 + 0x20) /* TIMER 1 */ macro
64 #define TIMER_BASE (0x20830000 + 0x10000) /* TIMER 1 */ macro
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/rk3399_rockchip-uboot/arch/arm/mach-rockchip/
H A Drockchip_debugger.c19 writel(TIMER_CLR_INT, TIMER_BASE + TIMER_INTSTATUS); in rockchip_debugger_isr()
33 writel(0, TIMER_BASE + TIMER_CTRL); in rockchip_debugger_init()
38 writel(load_count0, TIMER_BASE + TIMER_LOAD_COUNT0); in rockchip_debugger_init()
39 writel(load_count1, TIMER_BASE + TIMER_LOAD_COUNT1); in rockchip_debugger_init()
40 writel(TIMER_CLR_INT, TIMER_BASE + TIMER_INTSTATUS); in rockchip_debugger_init()
41 writel(TIMER_EN | TIMER_INT_EN, TIMER_BASE + TIMER_CTRL); in rockchip_debugger_init()
/rk3399_rockchip-uboot/arch/arm/cpu/arm1136/mx31/
H A Dtimer.c12 #define TIMER_BASE 0x53f90000 /* General purpose timer 1 */ macro
15 #define GPTCR __REG(TIMER_BASE) /* Control register */
16 #define GPTPR __REG(TIMER_BASE + 0x4) /* Prescaler register */
17 #define GPTSR __REG(TIMER_BASE + 0x8) /* Status register */
18 #define GPTCNT __REG(TIMER_BASE + 0x24) /* Counter register */
/rk3399_rockchip-uboot/test/rockchip/
H A Dtest-misc.c31 writel(TIMER_CLR_INT, TIMER_BASE + TIMER_INTSTATUS); in timer_irq_handler()
43 writel(0, TIMER_BASE + TIMER_CTRL); in timer_interrupt_test()
46 writel(gd->arch.timer_rate_hz, TIMER_BASE + TIMER_LOAD_COUNT0); in timer_interrupt_test()
47 writel(0, TIMER_BASE + TIMER_LOAD_COUNT1); in timer_interrupt_test()
48 writel(TIMER_CLR_INT, TIMER_BASE + TIMER_INTSTATUS); in timer_interrupt_test()
49 writel(TIMER_EN | TIMER_INT_EN, TIMER_BASE + TIMER_CTRL); in timer_interrupt_test()
/rk3399_rockchip-uboot/arch/arm/cpu/arm920t/ep93xx/
H A Dtimer.c43 struct timer_regs *timer_regs = (struct timer_regs *)TIMER_BASE; in read_timer()
94 struct timer_regs *timer_regs = (struct timer_regs *)TIMER_BASE; in timer_init()
/rk3399_rockchip-uboot/drivers/power/
H A Dcharge_animation.c375 writel(TIMER_CLR_INT, TIMER_BASE + TIMER_INTSTATUS); in autowake_timer_handler()
386 writel(0, TIMER_BASE + TIMER_CTRL); in autowakeup_timer_init()
389 writel((uint32_t)period, TIMER_BASE + TIMER_LOAD_COUNT0); in autowakeup_timer_init()
390 writel((uint32_t)(period >> 32), TIMER_BASE + TIMER_LOAD_COUNT1); in autowakeup_timer_init()
391 writel(TIMER_CLR_INT, TIMER_BASE + TIMER_INTSTATUS); in autowakeup_timer_init()
392 writel(TIMER_EN | TIMER_INT_EN, TIMER_BASE + TIMER_CTRL); in autowakeup_timer_init()
401 writel(0, TIMER_BASE + TIMER_CTRL); in autowakeup_timer_uninit()
/rk3399_rockchip-uboot/drivers/power/power_delivery/
H A Dtcpm.c807 writel(TIMER_CLR_INT, TIMER_BASE + TIMER_INTSTATUS); in tcpm_timer_irq()
817 writel(0, TIMER_BASE + TIMER_CTRL); in tcpm_timer_init()
820 writel((uint32_t)period, TIMER_BASE + TIMER_LOAD_COUNT0); in tcpm_timer_init()
821 writel((uint32_t)(period >> 32), TIMER_BASE + TIMER_LOAD_COUNT1); in tcpm_timer_init()
822 writel(TIMER_CLR_INT, TIMER_BASE + TIMER_INTSTATUS); in tcpm_timer_init()
823 writel(TIMER_EN | TIMER_INT_EN, TIMER_BASE + TIMER_CTRL); in tcpm_timer_init()
833 writel(0, TIMER_BASE + TIMER_CTRL); in tcpm_timer_uninit()
/rk3399_rockchip-uboot/arch/arm/include/asm/arch-ep93xx/
H A Dep93xx.h422 #define TIMER_BASE (EP93XX_APB_BASE | TIMER_OFFSET) macro