Home
last modified time | relevance | path

Searched refs:RK3588_PLLCON (Results 1 – 1 of 1) sorted by relevance

/rk3399_rockchip-uboot/drivers/clk/rockchip/
H A Dclk_pll.c424 #define RK3588_PLLCON(i) ((i) * 0x4) macro
483 rk_setreg(base + pll->con_offset + RK3588_PLLCON(1), in rk3588_pll_set_rate()
489 rk_clrsetreg(base + pll->con_offset + RK3588_PLLCON(1), in rk3588_pll_set_rate()
495 rk_clrsetreg(base + pll->con_offset + RK3588_PLLCON(2), in rk3588_pll_set_rate()
499 rk_clrreg(base + pll->con_offset + RK3588_PLLCON(1), in rk3588_pll_set_rate()
503 while (!(readl(base + pll->con_offset + RK3588_PLLCON(6)) & in rk3588_pll_set_rate()
582 con = readl(base + pll->con_offset + RK3588_PLLCON(1)); in rk3588_pll_get_rate()
587 con = readl(base + pll->con_offset + RK3588_PLLCON(2)); in rk3588_pll_get_rate()