Searched refs:PORT_LOGIC_LINK_WIDTH_MASK (Results 1 – 2 of 2) sorted by relevance
67 #define PORT_LOGIC_LINK_WIDTH_MASK (0x1f << 8) macro283 val &= ~PORT_LOGIC_LINK_WIDTH_MASK; in pcie_link_set_lanes()
133 #define PORT_LOGIC_LINK_WIDTH_MASK GENMASK(12, 8) macro134 #define PORT_LOGIC_LINK_WIDTH(n) FIELD_PREP(PORT_LOGIC_LINK_WIDTH_MASK, n)417 val &= ~PORT_LOGIC_LINK_WIDTH_MASK; in rk_pcie_configure()