Searched refs:PORT_LOGIC_LINK_WIDTH_8_LANES (Results 1 – 2 of 2) sorted by relevance
138 #define PORT_LOGIC_LINK_WIDTH_8_LANES PORT_LOGIC_LINK_WIDTH(0x8) macro429 val |= PORT_LOGIC_LINK_WIDTH_8_LANES; in rk_pcie_configure()
71 #define PORT_LOGIC_LINK_WIDTH_8_LANES (0x8 << 8) macro