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Searched refs:PORT_LOGIC_LINK_WIDTH_1_LANES (Results 1 – 2 of 2) sorted by relevance

/rk3399_rockchip-uboot/arch/arm/mach-rockchip/
H A Dspl_pcie_ep_boot.c68 #define PORT_LOGIC_LINK_WIDTH_1_LANES (0x1 << 8) macro
286 val |= PORT_LOGIC_LINK_WIDTH_1_LANES; in pcie_link_set_lanes()
/rk3399_rockchip-uboot/drivers/pci/
H A Dpcie_dw_rockchip.c135 #define PORT_LOGIC_LINK_WIDTH_1_LANES PORT_LOGIC_LINK_WIDTH(0x1) macro
420 val |= PORT_LOGIC_LINK_WIDTH_1_LANES; in rk_pcie_configure()