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Searched refs:PORT_LINK_MODE_2_LANES (Results 1 – 2 of 2) sorted by relevance

/rk3399_rockchip-uboot/arch/arm/mach-rockchip/
H A Dspl_pcie_ep_boot.c61 #define PORT_LINK_MODE_2_LANES (0x3 << 16) macro
270 val |= PORT_LINK_MODE_2_LANES; in pcie_link_set_lanes()
/rk3399_rockchip-uboot/drivers/pci/
H A Dpcie_dw_rockchip.c130 #define PORT_LINK_MODE_2_LANES PORT_LINK_MODE(0x3) macro
401 val |= PORT_LINK_MODE_2_LANES; in rk_pcie_configure()