Home
last modified time | relevance | path

Searched refs:PLL_PD (Results 1 – 8 of 8) sorted by relevance

/rk3399_rockchip-uboot/board/imx31_phycore/
H A Dlowlevel_init.S43 REG CCM_MPCTL, PLL_PD(0) | PLL_MFD(0xe) | PLL_MFI(9) | PLL_MFN(0xd)
45 REG CCM_SPCTL, PLL_PD(1) | PLL_MFD(0x43) | PLL_MFI(12) | PLL_MFN(1)
/rk3399_rockchip-uboot/include/configs/
H A Dmx31pdk.h152 #define CCM_MPCTL_SETUP_532MHZ (PLL_PD(0) | PLL_MFD(51) | PLL_MFI(10) | \
/rk3399_rockchip-uboot/board/freescale/mx31pdk/
H A Dlowlevel_init.S29 write32 CCM_SPCTL, PLL_PD(1) | PLL_MFD(4) | PLL_MFI(12) | PLL_MFN(1)
/rk3399_rockchip-uboot/drivers/video/drm/rk628/
H A Drk628_cru.c158 rk628_i2c_write(rk628, offset + CRU_CPLL_CON1, PLL_PD(1)); in rk628_cru_clk_set_rate_pll()
162 rk628_i2c_write(rk628, offset + CRU_CPLL_CON1, PLL_PD(0)); in rk628_cru_clk_set_rate_pll()
263 rk628_i2c_write(rk628, offset + CRU_CPLL_CON1, PLL_PD(0)); in rk628_cru_clk_set_rate_pll()
H A Drk628_cru.h27 #define PLL_PD(x) HIWORD_UPDATE(x, 13, 13) macro
/rk3399_rockchip-uboot/board/freescale/mx31ads/
H A Dlowlevel_init.S242 REG CCM_SPCTL, PLL_PD(1) | PLL_MFD(4) | PLL_MFI(12) | PLL_MFN(1)
/rk3399_rockchip-uboot/arch/arm/include/asm/arch-mx35/
H A Dimx-regs.h134 #define PLL_PD(x) (((x) & 0xf) << 26) macro
/rk3399_rockchip-uboot/arch/arm/include/asm/arch-mx31/
H A Dimx-regs.h581 #define PLL_PD(x) (((x) & 0xf) << 26) macro