1d08e5ca3SMagnus Lilja/* 2d08e5ca3SMagnus Lilja * (C) Copyright 2009 Magnus Lilja <lilja.magnus@gmail.com> 3d08e5ca3SMagnus Lilja * 4*1a459660SWolfgang Denk * SPDX-License-Identifier: GPL-2.0+ 5d08e5ca3SMagnus Lilja */ 6d08e5ca3SMagnus Lilja 7d08e5ca3SMagnus Lilja#include <config.h> 886271115SStefano Babic#include <asm/arch/imx-regs.h> 9d08e5ca3SMagnus Lilja#include <asm/macro.h> 10d08e5ca3SMagnus Lilja 11d08e5ca3SMagnus Lilja.globl lowlevel_init 12d08e5ca3SMagnus Liljalowlevel_init: 13d08e5ca3SMagnus Lilja /* Also setup the Peripheral Port Remap register inside the core */ 14d08e5ca3SMagnus Lilja ldr r0, =ARM_PPMRR /* start from AIPS 2GB region */ 15d08e5ca3SMagnus Lilja mcr p15, 0, r0, c15, c2, 4 16d08e5ca3SMagnus Lilja 17d08e5ca3SMagnus Lilja write32 IPU_CONF, IPU_CONF_DI_EN 18d08e5ca3SMagnus Lilja write32 CCM_CCMR, CCM_CCMR_SETUP 19d08e5ca3SMagnus Lilja 20d08e5ca3SMagnus Lilja wait_timer 0x40000 21d08e5ca3SMagnus Lilja 22d08e5ca3SMagnus Lilja write32 CCM_CCMR, CCM_CCMR_SETUP | CCMR_MPE 23d08e5ca3SMagnus Lilja write32 CCM_CCMR, (CCM_CCMR_SETUP | CCMR_MPE) & ~CCMR_MDS 24d08e5ca3SMagnus Lilja 25d08e5ca3SMagnus Lilja /* Set up clock to 532MHz */ 26d08e5ca3SMagnus Lilja write32 CCM_PDR0, CCM_PDR0_SETUP_532MHZ 27d08e5ca3SMagnus Lilja write32 CCM_MPCTL, CCM_MPCTL_SETUP_532MHZ 28d08e5ca3SMagnus Lilja 29d08e5ca3SMagnus Lilja write32 CCM_SPCTL, PLL_PD(1) | PLL_MFD(4) | PLL_MFI(12) | PLL_MFN(1) 30d08e5ca3SMagnus Lilja 31d08e5ca3SMagnus Lilja /* Set up MX31 DDR pins */ 32d08e5ca3SMagnus Lilja write32 IOMUXC_SW_PAD_CTL_SDCKE1_SDCLK_SDCLK_B, 0 33d08e5ca3SMagnus Lilja write32 IOMUXC_SW_PAD_CTL_CAS_SDWE_SDCKE0, 0 34d08e5ca3SMagnus Lilja write32 IOMUXC_SW_PAD_CTL_BCLK_RW_RAS, 0 35d08e5ca3SMagnus Lilja write32 IOMUXC_SW_PAD_CTL_CS2_CS3_CS4, 0x1000 36d08e5ca3SMagnus Lilja write32 IOMUXC_SW_PAD_CTL_DQM3_EB0_EB1, 0 37d08e5ca3SMagnus Lilja write32 IOMUXC_SW_PAD_CTL_DQM0_DQM1_DQM2, 0 38d08e5ca3SMagnus Lilja write32 IOMUXC_SW_PAD_CTL_SD29_SD30_SD31, 0 39d08e5ca3SMagnus Lilja write32 IOMUXC_SW_PAD_CTL_SD26_SD27_SD28, 0 40d08e5ca3SMagnus Lilja write32 IOMUXC_SW_PAD_CTL_SD23_SD24_SD25, 0 41d08e5ca3SMagnus Lilja write32 IOMUXC_SW_PAD_CTL_SD20_SD21_SD22, 0 42d08e5ca3SMagnus Lilja write32 IOMUXC_SW_PAD_CTL_SD17_SD18_SD19, 0 43d08e5ca3SMagnus Lilja write32 IOMUXC_SW_PAD_CTL_SD14_SD15_SD16, 0 44d08e5ca3SMagnus Lilja write32 IOMUXC_SW_PAD_CTL_SD11_SD12_SD13, 0 45d08e5ca3SMagnus Lilja write32 IOMUXC_SW_PAD_CTL_SD8_SD9_SD10, 0 46d08e5ca3SMagnus Lilja write32 IOMUXC_SW_PAD_CTL_SD5_SD6_SD7, 0 47d08e5ca3SMagnus Lilja write32 IOMUXC_SW_PAD_CTL_SD2_SD3_SD4, 0 48d08e5ca3SMagnus Lilja write32 IOMUXC_SW_PAD_CTL_SDBA0_SD0_SD1, 0 49d08e5ca3SMagnus Lilja write32 IOMUXC_SW_PAD_CTL_A24_A25_SDBA1, 0 50d08e5ca3SMagnus Lilja write32 IOMUXC_SW_PAD_CTL_A21_A22_A23, 0 51d08e5ca3SMagnus Lilja write32 IOMUXC_SW_PAD_CTL_A18_A19_A20, 0 52d08e5ca3SMagnus Lilja write32 IOMUXC_SW_PAD_CTL_A15_A16_A17, 0 53d08e5ca3SMagnus Lilja write32 IOMUXC_SW_PAD_CTL_A12_A13_A14, 0 54d08e5ca3SMagnus Lilja write32 IOMUXC_SW_PAD_CTL_A10_MA10_A11, 0 55d08e5ca3SMagnus Lilja write32 IOMUXC_SW_PAD_CTL_A7_A8_A9, 0 56d08e5ca3SMagnus Lilja write32 IOMUXC_SW_PAD_CTL_A4_A5_A6, 0 57d08e5ca3SMagnus Lilja write32 IOMUXC_SW_PAD_CTL_A1_A2_A3, 0 58d08e5ca3SMagnus Lilja write32 IOMUXC_SW_PAD_CTL_VPG0_VPG1_A0, 0 59d08e5ca3SMagnus Lilja 60d08e5ca3SMagnus Lilja /* Set up MX31 DDR Memory Controller */ 61d08e5ca3SMagnus Lilja write32 WEIM_ESDMISC, ESDMISC_MDDR_SETUP 62d08e5ca3SMagnus Lilja write32 WEIM_ESDCFG0, ESDCFG0_MDDR_SETUP 63d08e5ca3SMagnus Lilja 64d08e5ca3SMagnus Lilja /* Perform DDR init sequence */ 65d08e5ca3SMagnus Lilja write32 WEIM_ESDCTL0, ESDCTL_PRECHARGE 66d08e5ca3SMagnus Lilja write32 CSD0_BASE | 0x0f00, 0x12344321 67d08e5ca3SMagnus Lilja write32 WEIM_ESDCTL0, ESDCTL_AUTOREFRESH 68d08e5ca3SMagnus Lilja write32 CSD0_BASE, 0x12344321 69d08e5ca3SMagnus Lilja write32 CSD0_BASE, 0x12344321 70d08e5ca3SMagnus Lilja write32 WEIM_ESDCTL0, ESDCTL_LOADMODEREG 71d08e5ca3SMagnus Lilja write8 CSD0_BASE | 0x00000033, 0xda 72d08e5ca3SMagnus Lilja write8 CSD0_BASE | 0x01000000, 0xff 73d08e5ca3SMagnus Lilja write32 WEIM_ESDCTL0, ESDCTL_RW 74d08e5ca3SMagnus Lilja write32 CSD0_BASE, 0xDEADBEEF 75d08e5ca3SMagnus Lilja write32 WEIM_ESDMISC, ESDMISC_MDDR_RESET_DL 76d08e5ca3SMagnus Lilja 77d08e5ca3SMagnus Lilja mov pc, lr 78