Home
last modified time | relevance | path

Searched refs:PLL_BYPASS_MASK (Results 1 – 6 of 6) sorted by relevance

/rk3399_rockchip-uboot/arch/arm/mach-tegra/
H A Dcpu.c188 reg = PLL_BYPASS_MASK | (divm << pllinfo->m_shift); in pllx_set_rate()
209 reg &= ~PLL_BYPASS_MASK; in pllx_set_rate()
H A Dclock.c623 base_reg |= PLL_BYPASS_MASK; in clock_set_rate()
637 base_reg &= ~PLL_BYPASS_MASK; in clock_set_rate()
/rk3399_rockchip-uboot/arch/arm/mach-davinci/
H A Dlowlevel_init.S116 ldr r7, PLL_BYPASS_MASK
390 ldr r7, PLL_BYPASS_MASK
649 PLL_BYPASS_MASK: label
/rk3399_rockchip-uboot/drivers/video/drm/rk628/
H A Drk628_cru.h16 #define PLL_BYPASS_MASK BIT(15) macro
H A Drk628_cru.c98 bypass = (con0 & PLL_BYPASS_MASK) >> PLL_BYPASS_SHIFT; in rk628_cru_clk_get_rate_pll()
/rk3399_rockchip-uboot/arch/arm/include/asm/arch-tegra/
H A Dclk_rst.h242 #define PLL_BYPASS_MASK (1U << PLL_BYPASS_SHIFT) macro