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Searched refs:PLL_AUPLL (Results 1 – 8 of 8) sorted by relevance

/rk3399_rockchip-uboot/include/dt-bindings/clock/
H A Drockchip,rv1126b-cru.h13 #define PLL_AUPLL 3 macro
H A Drockchip,rk3576-cru.h16 #define PLL_AUPLL 5 macro
H A Drk3588-cru.h17 #define PLL_AUPLL 5 macro
/rk3399_rockchip-uboot/drivers/clk/rockchip/
H A Dclk_rv1126b.c46 [AUPLL] = PLL(pll_rk3328, PLL_AUPLL, RV1126B_PLL_CON(0),
62 RV1126B_CLK_DUMP(PLL_AUPLL, "aupll", true),
1481 case PLL_AUPLL: in rv1126b_clk_get_rate()
1613 case PLL_AUPLL: in rv1126b_clk_set_rate()
H A Dclk_rk3576.c73 [AUPLL] = PLL(pll_rk3588, PLL_AUPLL, RK3576_PLL_CON(96),
95 RK3576_CLK_DUMP(PLL_AUPLL, "aupll", true),
2090 case PLL_AUPLL: in rk3576_clk_get_rate()
2254 case PLL_AUPLL: in rk3576_clk_set_rate()
2448 else if (parent->id == PLL_AUPLL) in rk3576_dclk_vop_set_parent()
H A Dclk_rk3588.c58 [AUPLL] = PLL(pll_rk3588, PLL_AUPLL, RK3588_PLL_CON(96),
83 RK3588_CLK_DUMP(PLL_AUPLL, "aupll", true),
1583 case PLL_AUPLL: in rk3588_clk_get_rate()
1732 case PLL_AUPLL: in rk3588_clk_set_rate()
/rk3399_rockchip-uboot/arch/arm/dts/
H A Drk3576.dtsi1479 <&cru PLL_AUPLL>, <&cru CLK_UART_FRAC_0>,
3502 assigned-clock-parents = <&cru PLL_AUPLL>;
H A Drv1126b.dtsi748 <&cru PLL_AUPLL>, <&cru CLK_AUDIO_FRAC0_SRC>,