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Searched refs:PHY_REG (Results 1 – 7 of 7) sorted by relevance

/rk3399_rockchip-uboot/drivers/ram/rockchip/
H A Dsdram_phy_px30.c19 setbits_le32(PHY_REG(phy_base, 0x13), 1 << 4); in sdram_phy_dll_bypass_set()
20 clrbits_le32(PHY_REG(phy_base, 0x14), 1 << 3); in sdram_phy_dll_bypass_set()
23 setbits_le32(PHY_REG(phy_base, j), 1 << 4); in sdram_phy_dll_bypass_set()
24 clrbits_le32(PHY_REG(phy_base, j + 0x1), 1 << 3); in sdram_phy_dll_bypass_set()
29 setbits_le32(PHY_REG(phy_base, 0xa4), 0x1f); in sdram_phy_dll_bypass_set()
31 clrbits_le32(PHY_REG(phy_base, 0xa4), 0x1f); in sdram_phy_dll_bypass_set()
46 writel(tmp, PHY_REG(phy_base, j)); in sdram_phy_dll_bypass_set()
71 writel(cmd_drv, PHY_REG(phy_base, 0x11)); in sdram_phy_set_ds_odt()
72 clrsetbits_le32(PHY_REG(phy_base, 0x12), 0x1f << 3, cmd_drv << 3); in sdram_phy_set_ds_odt()
73 writel(clk_drv, PHY_REG(phy_base, 0x16)); in sdram_phy_set_ds_odt()
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H A Dsdram_rv1126.c571 clrbits_le32(PHY_REG(phy_base, 0x53), PHY_PD_DISB); in phy_pll_set()
572 while (!(readl(PHY_REG(phy_base, 0x90)) & PHY_PLL_LOCK)) { in phy_pll_set()
596 writel(fbdiv & 0xff, PHY_REG(phy_base, 0x50)); in phy_pll_set()
597 clrsetbits_le32(PHY_REG(phy_base, 0x51), PHY_PBDIV_BIT9_MASK, in phy_pll_set()
599 clrsetbits_le32(PHY_REG(phy_base, 0x51), PHY_POSTDIV_EN_MASK, in phy_pll_set()
602 clrsetbits_le32(PHY_REG(phy_base, 0x52), in phy_pll_set()
604 clrsetbits_le32(PHY_REG(phy_base, 0x53), in phy_pll_set()
1043 clrsetbits_le32(PHY_REG(phy_base, 0x100), 0x1f, phy_ca_drv); in set_ds_odt()
1044 clrsetbits_le32(PHY_REG(phy_base, 0x101), 0x1f, phy_ca_drv); in set_ds_odt()
1045 clrsetbits_le32(PHY_REG(phy_base, 0x102), 0x1f, phy_clk_drv); in set_ds_odt()
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H A Dsdram_rk3328.c126 clrbits_le32(PHY_REG(phy_base, 0xef), 1 << 7); in rkclk_configure_ddr()
266 gate_val = MAX(readl(PHY_REG(phy_base, 0xfb + i)), gate_val); in rx_deskew_switch_adjust()
270 clrsetbits_le32(PHY_REG(phy_base, 0x6e), 0xc, (deskew_val & 0x3) << 2); in rx_deskew_switch_adjust()
271 clrsetbits_le32(PHY_REG(phy_base, 0x6f), 0x7 << 4, in rx_deskew_switch_adjust()
279 clrsetbits_le32(PHY_REG(phy_base, 0x6e), 0x3, 1); in tx_deskew_switch_adjust()
H A Dsdram_px30.c248 bw = (readl(PHY_REG(phy_base, 0x0)) >> 4) & 0xf; in check_rd_gate()
263 gate[i] = readl(PHY_REG(phy_base, 0xfb + i)); in check_rd_gate()
386 setbits_le32(PHY_REG(phy_base, 7), 1 << 7); in enable_low_power()
/rk3399_rockchip-uboot/arch/arm/include/asm/arch-rockchip/
H A Dsdram_phy_px30.h15 #define PHY_REG(base, n) ((base) + 4 * (n)) macro
H A Dsdram_phy_rv1126.h92 #define PHY_REG(base, n) ((base) + 4 * (n)) macro
/rk3399_rockchip-uboot/drivers/video/drm/
H A Dinno_video_combo_phy.c35 #define PHY_REG(first, second) (FIRST_ADDRESS(first) | \ macro
337 u32 reg = PHY_REG(first, second) << 2; in phy_update_bits()