1*f520bb22SYouMin Chen /* SPDX-License-Identifier: GPL-2.0+ */ 2*f520bb22SYouMin Chen /* 3*f520bb22SYouMin Chen * Copyright (C) 2020 Rockchip Electronics Co., Ltd 4*f520bb22SYouMin Chen */ 5*f520bb22SYouMin Chen 6*f520bb22SYouMin Chen #ifndef _ASM_ARCH_SDRAM_RK1126_PHY_H 7*f520bb22SYouMin Chen #define _ASM_ARCH_SDRAM_RK1126_PHY_H 8*f520bb22SYouMin Chen 9*f520bb22SYouMin Chen /* PHY_REG0 */ 10*f520bb22SYouMin Chen #define DIGITAL_DERESET BIT(3) 11*f520bb22SYouMin Chen #define ANALOG_DERESET BIT(2) 12*f520bb22SYouMin Chen #define DIGITAL_RESET (0 << 3) 13*f520bb22SYouMin Chen #define ANALOG_RESET (0 << 2) 14*f520bb22SYouMin Chen 15*f520bb22SYouMin Chen /* PHY_REG1 */ 16*f520bb22SYouMin Chen #define PHY_DDR2 (0) 17*f520bb22SYouMin Chen #define PHY_LPDDR2 (1) 18*f520bb22SYouMin Chen #define PHY_DDR3 (2) 19*f520bb22SYouMin Chen #define PHY_LPDDR3 (3) 20*f520bb22SYouMin Chen #define PHY_DDR4 (4) 21*f520bb22SYouMin Chen #define PHY_DDR5 (5) 22*f520bb22SYouMin Chen #define PHY_BL_4 (0 << 3) 23*f520bb22SYouMin Chen #define PHY_BL_8_OR_16 BIT(3) 24*f520bb22SYouMin Chen 25*f520bb22SYouMin Chen /* PHY_REG2 */ 26*f520bb22SYouMin Chen #define PHY_DTT_EN BIT(0) 27*f520bb22SYouMin Chen #define PHY_DTT_DISB (0 << 0) 28*f520bb22SYouMin Chen #define PHY_WRITE_LEVELING_EN BIT(2) 29*f520bb22SYouMin Chen #define PHY_WRITE_LEVELING_DISB (0 << 2) 30*f520bb22SYouMin Chen #define PHY_SELECT_CS0 (2) 31*f520bb22SYouMin Chen #define PHY_SELECT_CS1 (1) 32*f520bb22SYouMin Chen #define PHY_SELECT_CS0_1 (0) 33*f520bb22SYouMin Chen #define PHY_WRITE_LEVELING_SELECTCS(n) ((n) << 6) 34*f520bb22SYouMin Chen #define PHY_DATA_TRAINING_SELECTCS(n) ((n) << 4) 35*f520bb22SYouMin Chen 36*f520bb22SYouMin Chen /* PHY_REGf */ 37*f520bb22SYouMin Chen #define PHY_DQ_WIDTH_MASK (0xf) 38*f520bb22SYouMin Chen 39*f520bb22SYouMin Chen /* PHY_REG51 */ 40*f520bb22SYouMin Chen #define PHY_PBDIV_BIT9_MASK BIT(0) 41*f520bb22SYouMin Chen #define PHY_PBDIV_BIT9_SHIFT (0) 42*f520bb22SYouMin Chen #define PHY_POSTDIV_EN_MASK BIT(7) 43*f520bb22SYouMin Chen #define PHY_POSTDIV_EN_SHIFT (7) 44*f520bb22SYouMin Chen 45*f520bb22SYouMin Chen /* PHY_REG52 */ 46*f520bb22SYouMin Chen #define PHY_PREDIV_MASK (0x1F) 47*f520bb22SYouMin Chen #define PHY_PREDIV_SHIFT (0) 48*f520bb22SYouMin Chen 49*f520bb22SYouMin Chen /* PHY_REG53*/ 50*f520bb22SYouMin Chen #define PHY_POSTDIV_MASK (0x7) 51*f520bb22SYouMin Chen #define PHY_POSTDIV_SHIFT (5) 52*f520bb22SYouMin Chen #define PHY_PD_DISB BIT(3) 53*f520bb22SYouMin Chen 54*f520bb22SYouMin Chen /* PHY_REG90 */ 55*f520bb22SYouMin Chen #define PHY_PLL_LOCK BIT(2) 56*f520bb22SYouMin Chen 57*f520bb22SYouMin Chen struct ca_skew { 58*f520bb22SYouMin Chen u32 a0_a3_a3_cke1_a_de_skew; 59*f520bb22SYouMin Chen u32 a1_ba1_null_cke0_b_de_skew; 60*f520bb22SYouMin Chen u32 a2_a9_a9_a4_a_de_skew; 61*f520bb22SYouMin Chen u32 a3_a15_null_a5_b_de_skew; 62*f520bb22SYouMin Chen u32 a4_a6_a6_ck_a_de_skew; 63*f520bb22SYouMin Chen u32 a5_a12_null_odt0_b_de_skew; 64*f520bb22SYouMin Chen u32 a6_ba2_null_a0_a_de_skew; 65*f520bb22SYouMin Chen u32 a7_a4_a4_odt0_a_de_skew; 66*f520bb22SYouMin Chen u32 a8_a1_a1_cke0_a_de_skew; 67*f520bb22SYouMin Chen u32 a9_a5_a5_a5_a_de_skew; 68*f520bb22SYouMin Chen u32 a10_a8_a8_clkb_a_de_skew; 69*f520bb22SYouMin Chen u32 a11_a7_a7_ca2_a_de_skew; 70*f520bb22SYouMin Chen u32 a12_rasn_null_ca1_a_de_skew; 71*f520bb22SYouMin Chen u32 a13_a13_null_ca3_a_de_skew; 72*f520bb22SYouMin Chen u32 a14_a14_null_csb1_b_de_skew; 73*f520bb22SYouMin Chen u32 a15_a10_null_ca0_b_de_skew; 74*f520bb22SYouMin Chen u32 a16_a11_null_csb0_b_de_skew; 75*f520bb22SYouMin Chen u32 a17_null_null_null_de_skew; 76*f520bb22SYouMin Chen u32 ba0_csb1_csb1_csb0_a_de_skew; 77*f520bb22SYouMin Chen u32 ba1_wen_null_cke1_b_de_skew; 78*f520bb22SYouMin Chen u32 bg0_odt1_odt1_csb1_a_de_skew; 79*f520bb22SYouMin Chen u32 bg1_a2_a2_odt1_a_de_skew; 80*f520bb22SYouMin Chen u32 cke0_casb_null_ca1_b_de_skew; 81*f520bb22SYouMin Chen u32 ck_ck_ck_ck_b_de_skew; 82*f520bb22SYouMin Chen u32 ckb_ckb_ckb_ckb_b_de_skew; 83*f520bb22SYouMin Chen u32 csb0_odt0_odt0_ca2_b_de_skew; 84*f520bb22SYouMin Chen u32 odt0_csb0_csb0_ca4_b_de_skew; 85*f520bb22SYouMin Chen u32 resetn_resetn_null_resetn_de_skew; 86*f520bb22SYouMin Chen u32 actn_cke_cke_ca3_b_de_skew; 87*f520bb22SYouMin Chen u32 null_null_null_null_de_skew; 88*f520bb22SYouMin Chen u32 csb1_ba0_null_null_de_skew; 89*f520bb22SYouMin Chen u32 odt1_a0_a0_odt1_b_de_skew; 90*f520bb22SYouMin Chen }; 91*f520bb22SYouMin Chen 92*f520bb22SYouMin Chen #define PHY_REG(base, n) ((base) + 4 * (n)) 93*f520bb22SYouMin Chen #endif /* _ASM_ARCH_SDRAM_RK1126_PHY_H */ 94