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Searched refs:PHYS_SDRAM_1 (Results 1 – 25 of 135) sorted by relevance

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/rk3399_rockchip-uboot/include/configs/
H A Dea20.h42 #define PHYS_SDRAM_1 DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */ macro
47 #define CONFIG_SYS_MEMTEST_START (PHYS_SDRAM_1 + 0x2000000)
50 #define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1 + 0x2000000 + 16*1024*1024)
107 #define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1 + 0x700000)
116 #define LINUX_BOOT_PARAM_ADDR (PHYS_SDRAM_1 + 0x100)
H A Dlegoev3.h36 #define PHYS_SDRAM_1 DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */ macro
41 #define CONFIG_SYS_MEMTEST_START (PHYS_SDRAM_1 + 0x2000000)
44 #define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1 + 0x2000000 + 16*1024*1024)
145 #define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1 + 0x700000)
154 #define LINUX_BOOT_PARAM_ADDR (PHYS_SDRAM_1 + 0x100)
H A Drcar-gen3-common.h54 #define PHYS_SDRAM_1 (0x40000000 + DRAM_RSV_SIZE) macro
62 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
66 #define PHYS_SDRAM_1 (0x40000000 + DRAM_RSV_SIZE) macro
70 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
H A Dstih410-b2260.h13 #define PHYS_SDRAM_1 0x40000000 macro
14 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
17 #define CONFIG_SYS_LOAD_ADDR PHYS_SDRAM_1 /* default load addr */
H A Dmx25pdk.h35 #define PHYS_SDRAM_1 0x80000000 macro
38 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
48 #define CONFIG_SYS_MEMTEST_START (PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE/2)
49 #define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE)
H A Dbcm_northstar2.h16 #define PHYS_SDRAM_1 V2M_BASE macro
21 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
25 #define CONFIG_SYS_INIT_SP_ADDR (PHYS_SDRAM_1 + 0x7ff00)
H A Domapl138_lcdk.h40 #define PHYS_SDRAM_1 DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */ macro
45 #define CONFIG_SYS_MEMTEST_START (PHYS_SDRAM_1 + 0x2000000)
48 #define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1 + 0x2000000 + 16*1024*1024)
235 #define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1 + 0x700000)
244 #define LINUX_BOOT_PARAM_ADDR (PHYS_SDRAM_1 + 0x100)
H A Dda850evm.h49 #define PHYS_SDRAM_1 DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */ macro
54 #define CONFIG_SYS_MEMTEST_START (PHYS_SDRAM_1 + 0x2000000)
57 #define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1 + 0x2000000 + 16*1024*1024)
244 #define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1 + 0x700000)
253 #define LINUX_BOOT_PARAM_ADDR (PHYS_SDRAM_1 + 0x100)
H A Dedb93xx.h138 #define PHYS_SDRAM_1 0x00000000 macro
141 #define PHYS_SDRAM_1 0xc0000000 macro
144 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
151 #define LINUX_BOOT_PARAM_ADDR (PHYS_SDRAM_1 + 0x100)
H A Dts4600.h24 #define PHYS_SDRAM_1 0x40000000 /* Base address */ macro
26 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
H A Dvexpress_aemv8a.h140 #define PHYS_SDRAM_1 (V2M_BASE) /* SDRAM Bank #1 */ macro
144 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
155 #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1
156 #define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE)
H A Dcalimain.h129 #define PHYS_SDRAM_1 DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */ macro
141 #define CONFIG_SYS_MEMTEST_START (PHYS_SDRAM_1 + 0x2000000)
191 #define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1 + 0x700000)
201 #define LINUX_BOOT_PARAM_ADDR (PHYS_SDRAM_1 + 0x100)
H A Dmx23_olinuxino.h17 #define PHYS_SDRAM_1 0x40000000 /* Base address */ macro
19 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
H A Dsansa_fuze_plus.h16 #define PHYS_SDRAM_1 0x40000000 /* Base address */ macro
18 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
H A Dxfi3.h16 #define PHYS_SDRAM_1 0x40000000 /* Base address */ macro
18 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
H A Dsc_sps_1.h20 #define PHYS_SDRAM_1 0x40000000 /* Base address */ macro
22 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
H A Dipam390.h41 #define PHYS_SDRAM_1 DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */ macro
46 #define CONFIG_SYS_MEMTEST_START (PHYS_SDRAM_1 + 0x2000000)
199 #define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1 + 0x700000)
208 #define LINUX_BOOT_PARAM_ADDR (PHYS_SDRAM_1 + 0x100)
H A Dmx23evk.h20 #define PHYS_SDRAM_1 0x40000000 /* Base address */ macro
22 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
H A Dbg0900.h14 #define PHYS_SDRAM_1 0x40000000 /* Base address */ macro
16 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
H A Dcolibri_pxa270.h100 #define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */ macro
109 #define CONFIG_SYS_LOAD_ADDR PHYS_SDRAM_1
110 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
H A Dintegrator-common.h75 #define PHYS_SDRAM_1 0x00000000 /* SDRAM Bank #1 */ macro
77 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
H A Dstv0991.h17 #define PHYS_SDRAM_1 0x00000000 macro
18 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
/rk3399_rockchip-uboot/board/samsung/smdkc100/
H A Dsmdkc100.c43 gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; in board_init()
50 gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE); in dram_init()
57 gd->bd->bi_dram[0].start = PHYS_SDRAM_1; in dram_init_banksize()
/rk3399_rockchip-uboot/board/cirrus/edb93xx/
H A Dedb93xx.c129 dram_bank_base[0] = PHYS_SDRAM_1; in dram_fill_bank_addr()
152 unsigned addr = PHYS_SDRAM_1; in dram_fill_bank_addr()
177 (PHYS_SDRAM_1 | UBOOT_MEMORYCNF_BANK_SIZE); in dram_init_banksize_int()
179 (PHYS_SDRAM_1 | UBOOT_MEMORYCNF_BANK_MASK); in dram_init_banksize_int()
181 (PHYS_SDRAM_1 | UBOOT_MEMORYCNF_BANK_COUNT); in dram_init_banksize_int()
/rk3399_rockchip-uboot/board/samsung/smdkv310/
H A Dsmdkv310.c41 gd->bd->bi_boot_params = (PHYS_SDRAM_1 + 0x100UL); in board_init()
47 gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE) in dram_init()
57 gd->bd->bi_dram[0].start = PHYS_SDRAM_1; in dram_init_banksize()
58 gd->bd->bi_dram[0].size = get_ram_size((long *)PHYS_SDRAM_1, in dram_init_banksize()

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