1e62b008fSLinus Walleij /* 2e62b008fSLinus Walleij * (C) Copyright 2012 3e62b008fSLinus Walleij * Linaro 4e62b008fSLinus Walleij * Linus Walleij <linus.walleij@linaro.org> 5e62b008fSLinus Walleij * Common ARM Integrator configuration settings 6e62b008fSLinus Walleij * 71a459660SWolfgang Denk * SPDX-License-Identifier: GPL-2.0+ 8e62b008fSLinus Walleij */ 9e62b008fSLinus Walleij 10e62b008fSLinus Walleij #define CONFIG_SYS_TEXT_BASE 0x01000000 11e62b008fSLinus Walleij #define CONFIG_SYS_MEMTEST_START 0x100000 12e62b008fSLinus Walleij #define CONFIG_SYS_MEMTEST_END 0x10000000 13e62b008fSLinus Walleij #define CONFIG_SYS_TIMERBASE 0x13000100 /* Timer1 */ 14e62b008fSLinus Walleij #define CONFIG_SYS_LOAD_ADDR 0x7fc0 /* default load address */ 15e62b008fSLinus Walleij #define CONFIG_SYS_LONGHELP 16e62b008fSLinus Walleij #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024) /* Size of malloc() pool */ 17e62b008fSLinus Walleij 18*3f394e70SLinus Walleij /* Serial port PL010/PL011 through the device model */ 19*3f394e70SLinus Walleij #define CONFIG_PL01X_SERIAL 20*3f394e70SLinus Walleij #define CONFIG_CONS_INDEX 0 21*3f394e70SLinus Walleij 22e62b008fSLinus Walleij #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ 23e62b008fSLinus Walleij #define CONFIG_SETUP_MEMORY_TAGS 24e62b008fSLinus Walleij #define CONFIG_MISC_INIT_R /* call misc_init_r during start up */ 25e62b008fSLinus Walleij 26e62b008fSLinus Walleij /* 27e62b008fSLinus Walleij * There are various dependencies on the core module (CM) fitted 28e62b008fSLinus Walleij * Users should refer to their CM user guide 29e62b008fSLinus Walleij */ 30e62b008fSLinus Walleij #include "armcoremodule.h" 31e62b008fSLinus Walleij 32e62b008fSLinus Walleij /* 33e62b008fSLinus Walleij * Initialize and remap the core module, use SPD to detect memory size 34e62b008fSLinus Walleij * If CONFIG_SKIP_LOWLEVEL_INIT is not defined & 35e62b008fSLinus Walleij * the core module has a CM_INIT register 36e62b008fSLinus Walleij * then the U-Boot initialisation code will 37e62b008fSLinus Walleij * e.g. ARM Boot Monitor or pre-loader is repeated once 38e62b008fSLinus Walleij * (to re-initialise any existing CM_INIT settings to safe values). 39e62b008fSLinus Walleij * 40e62b008fSLinus Walleij * This is usually not the desired behaviour since the platform 41e62b008fSLinus Walleij * will either reboot into the ARM monitor (or pre-loader) 42e62b008fSLinus Walleij * or continuously cycle thru it without U-Boot running, 43e62b008fSLinus Walleij * depending upon the setting of Integrator/CP switch S2-4. 44e62b008fSLinus Walleij * 45e62b008fSLinus Walleij * However it may be needed if Integrator/CP switch S2-1 46e62b008fSLinus Walleij * is set OFF to boot direct into U-Boot. 47e62b008fSLinus Walleij * In that case comment out the line below. 48e62b008fSLinus Walleij */ 49e62b008fSLinus Walleij #define CONFIG_CM_INIT 50e62b008fSLinus Walleij #define CONFIG_CM_REMAP 51e62b008fSLinus Walleij #define CONFIG_CM_SPD_DETECT 52e62b008fSLinus Walleij 53e62b008fSLinus Walleij /* 54e62b008fSLinus Walleij * The ARM boot monitor initializes the board. 55e62b008fSLinus Walleij * However, the default U-Boot code also performs the initialization. 56e62b008fSLinus Walleij * If desired, this can be prevented by defining SKIP_LOWLEVEL_INIT 57e62b008fSLinus Walleij * - see documentation supplied with board for details of how to choose the 58e62b008fSLinus Walleij * image to run at reset/power up 59e62b008fSLinus Walleij * e.g. whether the ARM Boot Monitor runs before U-Boot 60e62b008fSLinus Walleij */ 61e62b008fSLinus Walleij /* #define CONFIG_SKIP_LOWLEVEL_INIT */ 62e62b008fSLinus Walleij 63e62b008fSLinus Walleij /* 64e62b008fSLinus Walleij * The ARM boot monitor does not relocate U-Boot. 65e62b008fSLinus Walleij * However, the default U-Boot code performs the relocation check, 66e62b008fSLinus Walleij * and may relocate the code if the memory map is changed. 67e62b008fSLinus Walleij * If necessary this can be prevented by defining SKIP_RELOCATE_UBOOT 68e62b008fSLinus Walleij */ 69e62b008fSLinus Walleij /* #define SKIP_CONFIG_RELOCATE_UBOOT */ 70e62b008fSLinus Walleij 71e62b008fSLinus Walleij /* 72e62b008fSLinus Walleij * Physical Memory Map 73e62b008fSLinus Walleij */ 74e62b008fSLinus Walleij #define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ 75e62b008fSLinus Walleij #define PHYS_SDRAM_1 0x00000000 /* SDRAM Bank #1 */ 76e62b008fSLinus Walleij #define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB */ 77e62b008fSLinus Walleij #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 78e62b008fSLinus Walleij #define CONFIG_SYS_INIT_RAM_SIZE PHYS_SDRAM_1_SIZE 79e62b008fSLinus Walleij #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_SDRAM_BASE + \ 80e62b008fSLinus Walleij CONFIG_SYS_INIT_RAM_SIZE - \ 81e62b008fSLinus Walleij GENERATED_GBL_DATA_SIZE) 82e62b008fSLinus Walleij #define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_GBL_DATA_OFFSET 83a7b00a7bSLinus Walleij 84a7b00a7bSLinus Walleij /* 85a7b00a7bSLinus Walleij * FLASH and environment organization 86a7b00a7bSLinus Walleij * Top varies according to amount fitted 87a7b00a7bSLinus Walleij * Reserve top 4 blocks of flash 88a7b00a7bSLinus Walleij * - ARM Boot Monitor 89a7b00a7bSLinus Walleij * - Unused 90a7b00a7bSLinus Walleij * - SIB block 91a7b00a7bSLinus Walleij * - U-Boot environment 92a7b00a7bSLinus Walleij */ 93a7b00a7bSLinus Walleij #define CONFIG_SYS_FLASH_CFI 1 94a7b00a7bSLinus Walleij #define CONFIG_FLASH_CFI_DRIVER 1 95a7b00a7bSLinus Walleij #define CONFIG_SYS_FLASH_BASE 0x24000000 96a7b00a7bSLinus Walleij #define CONFIG_SYS_MAX_FLASH_BANKS 1 97a7b00a7bSLinus Walleij 98a7b00a7bSLinus Walleij /* Timeout values in ticks */ 99a7b00a7bSLinus Walleij #define CONFIG_SYS_FLASH_ERASE_TOUT (2 * CONFIG_SYS_HZ) /* Erase Timeout */ 100a7b00a7bSLinus Walleij #define CONFIG_SYS_FLASH_WRITE_TOUT (2 * CONFIG_SYS_HZ) /* Write Timeout */ 101a7b00a7bSLinus Walleij #define CONFIG_SYS_FLASH_PROTECTION /* The devices have real protection */ 102a7b00a7bSLinus Walleij #define CONFIG_SYS_FLASH_EMPTY_INFO /* flinfo indicates empty blocks */ 103