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Searched refs:PCIE_PORT_LINK_CONTROL (Results 1 – 2 of 2) sorted by relevance

/rk3399_rockchip-uboot/arch/arm/mach-rockchip/
H A Dspl_pcie_ep_boot.c58 #define PCIE_PORT_LINK_CONTROL 0x710 macro
263 val = readl(dbi_base + PCIE_PORT_LINK_CONTROL); in pcie_link_set_lanes()
279 writel(val, dbi_base + PCIE_PORT_LINK_CONTROL); in pcie_link_set_lanes()
/rk3399_rockchip-uboot/drivers/pci/
H A Dpcie_dw_rockchip.c120 #define PCIE_PORT_LINK_CONTROL 0x710 macro
391 val = readl(pci->dbi_base + PCIE_PORT_LINK_CONTROL); in rk_pcie_configure()
413 writel(val, pci->dbi_base + PCIE_PORT_LINK_CONTROL); in rk_pcie_configure()